Patents Examined by Long Pham
  • Patent number: 11923342
    Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanguk Han, Chajea Jo, Hyoeun Kim, Sunkyoung Seo
  • Patent number: 11923343
    Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaekyung Yoo, Jayeon Lee, Jae-eun Lee, Yeongkwon Ko, Jin-woo Park, Teak Hoon Lee
  • Patent number: 11915971
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11916031
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11916071
    Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok
  • Patent number: 11908806
    Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ho Kim, Ji Hwang Kim, Hwan Pil Park, Jong Bo Shim
  • Patent number: 11908729
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11910680
    Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array in a first direction and a second direction, the first direction intersecting with the second direction. The display substrate further includes data lines extended in the first direction, and the data lines are connected in one-to-one correspondence with the sub-pixels in columns in each row of sub-pixels, so as to provide data signals respectively; the display substrate further includes auxiliary electrode lines extended in the first direction which are configured to be electrically connected with a second electrode of the light emitting element to provide a second power voltage; each of the auxiliary electrode lines is spaced from any one of the plurality of data lines by at least one column of sub-pixels.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: February 20, 2024
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Yuan, Yongqian Li, Meng Li, Zhidong Yuan, Dacheng Zhang, Lang Liu
  • Patent number: 11901115
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
  • Patent number: 11901365
    Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11894315
    Abstract: An electronic system in package, including at least: a support; one or more chips mechanically and electrically coupled to a front face of the support; an encapsulation material covering the front face of the support and encapsulating the chip(s); several side protection elements, comprising an opaque material and laterally surrounding the chip(s) and configured to form a barrier at least against laser attacks made through side faces of the electronic system in package that are substantially perpendicular to the front face of the support; and wherein the side protection elements are disposed in the encapsulation material or in one or more first blocks of material distinct from the support and disposed in the encapsulation material.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 6, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thibaut Sohier, Stephan Borel
  • Patent number: 11894343
    Abstract: A semiconductor device is vertically mounted on a medium such as a printed circuit board (PCB). The semiconductor device comprises a block of semiconductor dies, mounted in a vertical stack without offset. Once formed and encapsulated, side grooves may be formed in the device exposing electrical conductors of each die within the device. The electrical conductors exposed in the grooves mount to electrical contacts on the medium to electrically couple the semiconductor device to the medium.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xianlu Cui, Junrong Yan, Wei Liu, Zhonghua Qian
  • Patent number: 11894323
    Abstract: A packaged radio-frequency device can include a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The packaging substrate may include a first component mounted on the first side and a first overmold structure implemented on the first side, the first overmold structure substantially encapsulating the first component. The packaging substrate may further include a set of through-mold connections implemented on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins, a second component mounted on the second side of the packaging substrate, the second component being located in an area of the second side configured to implement a redundant ground pad or a redundant portion of a ground pad, and a second overmold structure substantially encapsulating one or more of the second component or the set of through-mold connections.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: February 6, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Robert Francis Darveaux, Anthony James Lobianco
  • Patent number: 11894295
    Abstract: Process for manufacturing a chip-card module. It includes one or more operations in which a meltable solder is deposited on connection pads formed in a layer of electrically conductive material located on the back side of a dielectric substrate, and at least one electronic component is connected to these connection pads by reflowing the solder. Chip-card module obtained using this process. Chip card including such a module.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 6, 2024
    Assignee: Linxens Holding
    Inventors: Christophe Mathieu, Guillaume Gimbert
  • Patent number: 11887943
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11881446
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Pei Cheng Fan
  • Patent number: 11876031
    Abstract: A semiconductor package includes at least one semiconductor device mounted on a first substrate, a thermosetting resin layer on the at least one semiconductor device, the thermosetting resin layer including an irreversible thermochromic pigment, a metal plate on the thermosetting resin layer, and a molding member surrounding the at least one semiconductor device at least in a lateral direction and being in contact with the thermosetting resin layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joungphil Lee, Wonkeun Kim, Mihyae Park
  • Patent number: 11869920
    Abstract: An ultra-small light-emitting diode (LED) electrode assembly having an improved luminance is provided. More particularly, an ultra-small LED electrode assembly in which light, which is blocked by an electrode and cannot be extracted, is minimized, an ultra-small LED device is connected to an ultra-small electrode without a defect such as an electrical short-circuit, and a very excellent luminance is exhibited even at a direct current (DC) driving voltage, and a method of manufacturing the same are provided.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yun Jae Eo, Yeon Goog Sung
  • Patent number: 11869849
    Abstract: A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the first bonding wires, the second bonding wires, and the insulating material. The metal layer and the second bonding wires constitute an electromagnetic interference (EMI) shielding structure.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 9, 2024
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 11862734
    Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang