Patents Examined by Long Pham
  • Patent number: 11374165
    Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a chemical mechanical polishing process to improve surface roughness. An magnetic tunnel junction deposition is then performed over the bottom electrode buff layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 28, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Sajjad Amin Hassan, Mahendra Pakala, Jaesoo Ahn
  • Patent number: 11373901
    Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: June 28, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Lin, Chich-Neng Chang, Bin-Siang Tsai
  • Patent number: 11373983
    Abstract: A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: June 28, 2022
    Assignee: CCS Technology Corporation
    Inventors: Tung-Po Sung, Chang-Cheng Lo
  • Patent number: 11374169
    Abstract: A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Baohua Niu, Ji-Feng Ying
  • Patent number: 11367652
    Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 21, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 11362044
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 14, 2022
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yung-Chang Lien
  • Patent number: 11362103
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Gianpietro Carnevale
  • Patent number: 11355450
    Abstract: A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; a plurality of first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; a plurality of second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the plurality of first bonding wires, the plurality of second bonding wires, and the insulating material. The metal layer and the plurality of second bonding wires constitute an electromagnetic interference (EMI) shielding structure.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: June 7, 2022
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 11342255
    Abstract: A semiconductor package device includes an interposer die having a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a first semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the first semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side. Each of the plurality of TSVs includes a sidewall tapering from a first end near the second redistribution layer to a second end near the first redistribution layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11335665
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
  • Patent number: 11335725
    Abstract: A method for fabricating an optical sensor includes: forming, over a substrate, a first material layer comprising a first alloy of germanium and silicon having a first germanium composition; forming, over the first material layer, a graded material layer comprising germanium and silicon; and forming, over the graded material layer, a second material layer comprising a second alloy of germanium and silicon having a second germanium composition. The first germanium composition is lower than the second germanium composition and a germanium composition of the graded material layer is between the first germanium composition and the second germanium composition and varies along a direction perpendicular to the substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 17, 2022
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen
  • Patent number: 11335656
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11322610
    Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 11322517
    Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ho Bin, Il Young Kwon, Il Do Kim
  • Patent number: 11322513
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Patent number: 11322394
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11322428
    Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11322643
    Abstract: An optoelectronic device comprising a semiconductor structure includes a p-type active region, an n-type active region, and an i-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell can comprise a layer of GaN and a layer of AlN. In some cases, a combined thickness of the layers comprising the unit cells in the i-type active region is thicker than a combined thickness of the unit cells in the n-type active region, and is thicker than a combined thickness of the unit cells in the p-type active region. The layers in the unit cells in each of the three regions can all have thicknesses that are less than or equal to a critical layer thickness required to maintain elastic strain.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 3, 2022
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 11322598
    Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: May 3, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: YI-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11309255
    Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra