Abstract: A semiconductor package includes a base substrate, and a first package and a second package mounted apart from each other on an upper surface of the base substrate in a horizontal directions. The second package includes, on each surface thereof, connection pads corresponding to a package ball map including cells, arranged in a plurality of rows and a plurality of columns, each of which has one signal arranged therein. The package ball map includes a first signal, or a data signal, arranged in at least some cells among the cells of the package ball map, and a second signal, or a command or address signal, and the first signal is arranged apart from the second signal.

Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method of the semiconductor device includes forming a sacrificial group including a layer above the doped semiconductor layer, forming a stack structure above the sacrificial group, forming a slit passing through the stack structure, forming a spacer insulating layer over a sidewall of the slit, forming a horizontal space by removing the sacrificial group through the slit, forming a semiconductor pattern over a surface of the horizontal space to define a gap in the horizontal space, and forming an impurity region in the semiconductor pattern.

Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Abstract: A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

Abstract: A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.

Abstract: A device includes at least one semiconductor device; a package support configured to support the at least one semiconductor device; electrical connection portions having at least one of the following: electrical connection portions extending from the package support, electrical connection portions configured as a bond wire device connection, electrical connection portions configured as a bump ball connection, and/or electrical connection portions configured as a stud bump connection. Where the electrical connection portions connect between the at least one semiconductor device and the package support.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor module, a reorientation layer, a second semiconductor module and a plurality of jointing materials. The first semiconductor module has at least one first conductive structure and at least one second conductive structure. The reorientation layer covers part of the second conductive structure to form an opening. The second semiconductor module has at least one third conductive structure and at least one fourth conductive structure. The jointing materials are disposed between the first conductive structure and the third conductive structure, and disposed in the opening.

Abstract: A micro light-emitting diode transfer device and a method of transferring thereof are provided. The micro light-emitting diode transfer device includes an operating board, a light source generator, and a photomagnetic substrate. The light source generator is disposed above the operating board and includes a plurality of light emitting units, each of the light emitting units comprises a light emitting side, and the light emitting side faces the operating board. The photomagnetic substrate includes a plurality of photomagnetic units, which attract micro light-emitting diodes.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body with first conductive layers and first insulating layers alternately stacked. The stacked body includes a staircase portion in which the first conductive layers are in a staircase shape. A columnar portion extends in a stacking direction through the stacked body at the staircase portion. The columnar portion includes a semiconductor layer, a second insulating layer covering a side wall of the semiconductor layer, and a third insulating layer that covers the second insulating layer. The third insulating layer includes a material different from the second insulating layer and includes flanged portions that protrude from a sidewall thereof toward the first conductive layers at corresponding height positions.

Abstract: A package structure is disclosed. The package structure includes a first substrate, a second substrate, a gap, and a directing structure. The second substrate is disposed under the first substrate. The gap is between the first substrate and the second substrate. The gap includes a first region and a second region. The first region is configured to accommodate a filling material. The directing structure is disposed in a flow path of the filling material and configured to reduce a migration of the filling material from the first region to the second region.

Abstract: A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.

Abstract: Light trapping pixels, devices incorporating such pixels, and various associated methods are provided. In one aspect, for example, a light trapping pixel device can include a light sensitive pixel having a light incident surface, a backside surface opposite the light incident surface, and a peripheral sidewall disposed into at least a portion of the pixel and extending at least substantially around the pixel periphery. The pixel can also include a backside light trapping material substantially covering the backside surface and a peripheral light trapping material substantially covering the peripheral sidewall. The light contacting the backside light trapping material or the peripheral light trapping material is thus reflected back toward the pixel.

Abstract: A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies connecting IC dies on adjacent die stacks. In one example, a chip package includes an interconnect routing structure, a first die stack and a second die stack. The first die stack includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The second die stack also includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The first bridge die is electrically and mechanically coupled to the top dies of the first and second die stacks. The first bridge die having solid state circuitry that connects circuitries of the top dies of the first and second die stacks.

Abstract: A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

Abstract: Disclosed is a semiconductor package comprising a solder ball, a printed circuit board on the solder ball, a bump on the printed circuit board, and a semiconductor chip on the bump. The printed circuit board includes a base substrate, a low-k dielectric layer that penetrates the base substrate, a connection conductive structure electrically connected to the bump and surrounded by the low-k dielectric layer, and a lower conductive structure electrically connected to the solder ball and the connection conductive structure. A top surface of the lower conductive structure is in contact with a first bottom surface of the low-k dielectric layer.

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Abstract: A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical

Abstract: In one example, an electronic device comprises a substrate comprising a top side, a bottom side, a lateral side, and a conductive structure, a first electronic component over the top side of the substrate and coupled with the conductive structure, an encapsulant contacting the top side of the substrate, the bottom side of the substrate, and the lateral side of the substrate, a lid over the first electronic component and over the encapsulant, and a second electronic component over the top side of the substrate and coupled with the conductive structure, wherein the second electronic component is between the first electronic component and the lateral side of the substrate. Other examples and related methods are also disclosed herein.