Patents Examined by Long Pham
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Patent number: 12137563Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.Type: GrantFiled: January 19, 2023Date of Patent: November 5, 2024Assignee: SK hynix Inc.Inventor: Kang Sik Choi
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Patent number: 12136571Abstract: Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.Type: GrantFiled: July 28, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Jhon Jhy Liaw
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Patent number: 12137612Abstract: An organic photodetector comprising a photosensitive organic layer comprising an electron donor and an electron acceptor wherein the electron acceptor is a compound of formula (I): EAG-EDG-EAG??(I) wherein each EAG is an electron accepting group; and EDG is an electron-donating group of formula (II) or (III): A photosensor may comprise the organic photodetector and a light source, e.g. a near infra-red light source.Type: GrantFiled: December 15, 2020Date of Patent: November 5, 2024Assignee: Sumitomo Chemical Company LimitedInventors: Kiran Kamtekar, Sophie Jones, Nir Yaacobi-Gross
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Patent number: 12132007Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: GrantFiled: January 31, 2023Date of Patent: October 29, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongwan Kim, Kyong Hwan Koh, Juhyeon Oh, Yongkwan Lee
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Patent number: 12125760Abstract: A method of manufacturing an electronic package structure is disclosed. A solder mask layer is formed on an upper surface of a substrate. A recessed area is formed in the solder mask layer. An electronic component is mounted on the substrate. Pads are disposed on the upper surface of the substrate. The pads respectively correspond to the bumps on a first surface of the electronic component. The pads are electrically connected to the bumps. A heat treatment is performed to make the first surface close to the substrate and form a cavity in the recessed area. The cavity is between the first surface of the electronic component, the solder mask layer and the upper surface of the substrate.Type: GrantFiled: February 23, 2023Date of Patent: October 22, 2024Assignee: RichWave Technology Corp.Inventor: Yu-Lung Wen
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Patent number: 12125890Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.Type: GrantFiled: July 26, 2023Date of Patent: October 22, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Patent number: 12119310Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.Type: GrantFiled: June 15, 2023Date of Patent: October 15, 2024Assignee: STMicroelectronics (Rousset) SASInventor: Pascal Fornara
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Patent number: 12113029Abstract: A first molded resin containing first insulating fillers having particle sizes smaller than the opening size of a wire mesh is formed inside the wire mesh to seal a semiconductor chip, bonding wires, and bond pads, and a second molded resin containing second insulating fillers having particle sizes larger than the opening size of the wire mesh is formed outside the wire mesh to seal the semiconductor ship, the bonding wires, and the bond pads via the first molded resin and the wire mesh. This allows for reducing warpage during solder mounting and for improving productivity.Type: GrantFiled: April 5, 2019Date of Patent: October 8, 2024Assignee: Mitsubishi Electric CorporationInventor: Tatsuto Nishihara
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Patent number: 12113048Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.Type: GrantFiled: December 29, 2022Date of Patent: October 8, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
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Patent number: 12113003Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.Type: GrantFiled: July 3, 2023Date of Patent: October 8, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei Cheng Fan
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Patent number: 12107026Abstract: A circuit arrangement has a chip arrangement in the form of an embedded Wafer Level Ball Grid Array (eWLB) arrangement with solder contacts on one side and a thermal interface on a side of the chip arrangement facing away from the solder contacts which is designed to dissipate heat from the semiconductor chip. In examples, the thermal interface has a thermally and electrically conductive material, wherein in a top view of the chip arrangement, a contact area in which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the fan-out area. In examples, the thermal interface has at least one RF absorption layer which is designed to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.Type: GrantFiled: December 6, 2021Date of Patent: October 1, 2024Assignee: Infineon Technologies AGInventors: Raphael Hellwig, Philip Amos, Walter Hartner
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Patent number: 12100734Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.Type: GrantFiled: October 6, 2022Date of Patent: September 24, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Patent number: 12101962Abstract: A display device includes a display panel and a light control layer disposed on the display panel. The light control layer includes a base portion, a coloring agent having a maximum absorption wavelength in a wavelength range equal to or greater than about 580 nm and equal to or smaller than about 600 nm, and a desiccant.Type: GrantFiled: November 16, 2021Date of Patent: September 24, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jeong Myo Sim, Kyunghee Lee, Mihwa Lee
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Patent number: 12094794Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.Type: GrantFiled: November 10, 2022Date of Patent: September 17, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Patent number: 12087596Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.Type: GrantFiled: July 15, 2021Date of Patent: September 10, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keishi Okamoto, Akihiro Horibe, Hiroyuki Mori
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Patent number: 12087652Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.Type: GrantFiled: August 9, 2022Date of Patent: September 10, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
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Patent number: 12087643Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.Type: GrantFiled: July 15, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shiu-Ko Jangjian, Tzu-Kai Lin, Chi-Cherng Jeng
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Patent number: 12087854Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.Type: GrantFiled: September 6, 2022Date of Patent: September 10, 2024Assignee: Wolfspeed, Inc.Inventors: Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Kijeong Han, Edward Robert Van Brunt
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Patent number: 12076830Abstract: A polishing method capable of terminating polishing of a substrate, such as a wafer, at a preset polishing time is disclosed. The polishing method includes: polishing a substrate by pressing the substrate against a polishing surface of a polishing pad, while regulating a temperature of the polishing surface by a heat exchanger; calculating a target polishing rate required for an actual polishing time to coincide with a target polishing time, the actual polishing time being a time duration from start of polishing the substrate until a film thickness of the substrate reaches a target thickness; determining a target temperature of the polishing surface that can achieve the target polishing rate; and during polishing of the substrate, changing a temperature of the polishing surface to the target temperature by the heat exchanger.Type: GrantFiled: March 22, 2023Date of Patent: September 3, 2024Assignee: EBARA CORPORATIONInventor: Masashi Kabasawa
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Patent number: 12080698Abstract: A semiconductor package includes an interposer substrate; an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate, a chip stack on a bottom surface of the interposer substrate and including a plurality of stacked lower semiconductor chips, wherein each of the lower semiconductor chips includes a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate, a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip, and a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias. The upper semiconductor chip is electrically connected through the interposer substrate to the through vias.Type: GrantFiled: January 5, 2022Date of Patent: September 3, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Dongjoo Choi