Abstract: A semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region electrically connected to the first base plate and a second interconnection region; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer.

Abstract: A polymer compound for use in an electroluminescent device may improve the durability (particularly the luminescence lifespan). The polymer compound includes Structural Unit (A) represented by Chemical Formula (1). In Chemical Formula (1), the definition of each substituent is as described in the detailed description.

Abstract: The present technology relates to a semiconductor apparatus that makes it possible to make a sensor-chip package smaller in size, where a Peltier element is arranged in the sensor-chip package. The semiconductor apparatus includes a package that includes a concave portion; a sensor chip that is arranged in the concave portion; and a Peltier element that is arranged between the sensor chip and the package. A back-surface terminal and an upper-surface terminal are electrically connected to each other through a conductive resin, the back-surface terminal being formed on a back surface of a lower substrate of the Peltier element, the upper-surface terminal being formed on an upper surface of the concave portion to face the back-surface terminal. The present technology is applicable to, for example, a semiconductor apparatus that includes a built-in SWIR image sensor.

Abstract: According to one embodiment, a wiring board, includes a conductive layer on a first surface and an insulating layer covering a portion of the conductive layer. The conductive layer includes a first connection portion exposed from the insulating layer and having a first wettability to solder, a lead-out portion connected to the first connection portion and exposed from the insulating layer and having a second wettability to solder, and a wiring portion connected to the first connection portion via the lead-out portion and covered with the insulating layer. In some examples, the first connection portion may be coated with a gold layer and the conductive layer may be copper or a copper alloy material.

Abstract: A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.

Abstract: A composition comprising an electron donor a fullerene electron acceptor and a non-fullerene electron acceptor wherein the non-fullerene electron acceptor is a compound of formula (I): wherein each EAG is an electron accepting group; and EDG is an electron-donating group of formula (II) or (III): The composition may be used as a photosensitive layer of an organic photodetector.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Abstract: A semiconductor package includes a package substrate, substrate pads provided on a top surface of the package substrate, at least one core ball on at least one of the substrate pads, a redistribution substrate provided on the top surface of the package substrate, and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate is electrically connected to the package substrate through a plurality of solder balls provided on a bottom surface of the redistribution substrate. The at least one core ball is electrically connected to the redistribution substrate. A diameter of the at least one core ball is greater than a diameter of each of the plurality of solder balls.

Abstract: An example an IC package including a liner for promotion of mold adhesion includes a conductive structure on a support surface; a mold material at least partially encasing the conductive structure; and a liner on a surface of the conductive structure between the surface of the conductive structure and the mold material, wherein the liner comprises a material including silicon and nitrogen.

Abstract: Disclosed are apparatuses and techniques for fabricating single or multi-die packages with sealed enclosures. In one or more aspects an apparatus includes a die; a perimeter metallization disposed on a perimeter of the die; a package substrate; and a seal coupled to the perimeter metallization and the package substrate, configured to seal the die to the package substrate.

Abstract: A composite interposer includes a local-silicon-interconnect-containing (LSI-containing) interposer that includes a local silicon interconnect (LSI) bridge; and an organic interposer located on the LSI-containing interposer, including redistribution dielectric layers embedding redistribution wiring interconnects and a metallic counter-deformation structure. The metallic counter-deformation structure includes a plurality of metallic via structures; a first metallic plate located on a first side of the plurality of metallic via structures; and a second metallic plate located on a second side of the plurality metallic via structures and vertically spaced from the first metallic plate.

Abstract: A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.

Abstract: A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.

Abstract: A semiconductor package an interposer disposed on a substrate, a recess recessed from an upper surface of the interposer, a connection structure disposed inside the recess, a first post disposed on the upper surface of the interposer and electrically connected to the interposer, a second post disposed on an upper surface of the connection structure and electrically connected to the connection structure, a first lower semiconductor chip disposed between the first and second posts and disposed on the upper surface of the interposer and the upper surface of the connection structure. The first lower semiconductor chip is electrically connected to the second post through the connection structure, and a first upper semiconductor chip is disposed on an upper surface of the first lower semiconductor chip. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second post and the connection structure.

Abstract: A power-converter module has a switching Printed Circuit Board (PCB) with power transistors generating heat. Ground, an input power supply, and an output power supply to the power transistors connect through metal traces on the switching PCB directly to interposer heat sinks that are soldered to the switching PCB. Copper bars attached to the bottoms of interposer heat sinks fit in holes in a system PCB to make connections. The metal traces and interposer heat sinks carry supply or ground currents and heat away from the power transistors. These power and ground currents continue from the interposer heat sinks through the copper bars to the system PCB. An interposer PCB has soler pads and solder balls to carry control signals from the system PCB to the switching PCB, bypassing the interposer heat sinks. Copper bars can be sintered, soldered, or welded to or integral with the interposer heat sinks.

Abstract: A semiconductor package includes a base substrate, and a first package and a second package mounted apart from each other on an upper surface of the base substrate in a horizontal directions. The second package includes, on each surface thereof, connection pads corresponding to a package ball map including cells, arranged in a plurality of rows and a plurality of columns, each of which has one signal arranged therein. The package ball map includes a first signal, or a data signal, arranged in at least some cells among the cells of the package ball map, and a second signal, or a command or address signal, and the first signal is arranged apart from the second signal.

Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method of the semiconductor device includes forming a sacrificial group including a layer above the doped semiconductor layer, forming a stack structure above the sacrificial group, forming a slit passing through the stack structure, forming a spacer insulating layer over a sidewall of the slit, forming a horizontal space by removing the sacrificial group through the slit, forming a semiconductor pattern over a surface of the horizontal space to define a gap in the horizontal space, and forming an impurity region in the semiconductor pattern.

Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Abstract: A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.