Patents Examined by Long Pham
  • Patent number: 11031302
    Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Chih-Long Chiang, Kuo Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang
  • Patent number: 11031491
    Abstract: A normally-off first gate channel region is provided on a first main surface side, in a region in a p base between an n base and an n emitter connected to an emitter electrode. On and off of the first gate channel region is controlled by a voltage of a first gate electrode. A normally-on second gate channel region is provided on a second main surface side, by an n-type region between an n collector electrically connected to a collector electrode and the n base. On and off of the second gate channel region is controlled by a voltage of a second gate electrode.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Patent number: 11024570
    Abstract: A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 1, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Hsin Chang, Tsu-Hsiu Wu, Tsung-Yueh Tsai
  • Patent number: 11024740
    Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11024602
    Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Patent number: 11024650
    Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Chen, Chih-Hao Wang
  • Patent number: 11018229
    Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Manuj Nahar
  • Patent number: 11018100
    Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
  • Patent number: 11011604
    Abstract: A device includes a first gate structure positioned above an active region defined in a semiconducting substrate. A first spacer is positioned adjacent the first gate structure. First conductive source/drain contact structures are positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first recessed portion of the first conductive source/drain contact structures is positioned at a first axial position along the first gate structure. A second recessed portion of the first conductive source/drain contact structures is positioned at a second axial position along the gate structure. A dielectric cap layer is positioned above the first and second recessed portions. A first conductive contact contacts the first gate structure in the first axial position. The dielectric cap layer above the first recessed portion is positioned adjacent the first conductive contact.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 18, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hui Zang, Min-Hwa Chi
  • Patent number: 11011472
    Abstract: The present invention discloses a self-aligned register structure for base polysilicon and a preparation method thereof. The self-aligned register structure comprises a silicon substrate having a partially oxidized region of SiO2 medium, a SiO2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO2 medium protective layer, the adjacent base polysilicon layers are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 18, 2021
    Assignee: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 55 RESEARCH INSTITUTE
    Inventors: Hongjun Liu, Xianwei Ying, Yangyang Zhao, Guoxing Sheng
  • Patent number: 11004945
    Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Michael Hutzler
  • Patent number: 10991664
    Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: April 27, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 10985033
    Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: April 20, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10985169
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 20, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Koichi Matsuno, Johann Alsmeier
  • Patent number: 10985166
    Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Patent number: 10985198
    Abstract: Light trapping pixels, devices incorporating such pixels, and various associated methods are provided. In one aspect, for example, a light trapping pixel device can include a light sensitive pixel having a light incident surface, a backside surface opposite the light incident surface, and a peripheral sidewall disposed into at least a portion of the pixel and extending at least substantially around the pixel periphery. The pixel can also include a backside light trapping material substantially covering the backside surface and a peripheral light trapping material substantially covering the peripheral sidewall. The light contacting the backside light trapping material or the peripheral light trapping material is thus reflected back toward the pixel.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 20, 2021
    Assignee: SiOnyx, LLC
    Inventors: Martin U. Pralle, Jeffrey McKee, Jason Sickler
  • Patent number: 10978457
    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 13, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Yu-Hsiang Hung, Ming-Te Wei
  • Patent number: 10978432
    Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kilsoo Kim
  • Patent number: 10974433
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Patent number: 10971519
    Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 6, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Zih-Song Wang, Chen-Liang Ma