Patents Examined by Long Pham
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Patent number: 11967566Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.Type: GrantFiled: December 21, 2022Date of Patent: April 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
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Patent number: 11967525Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: GrantFiled: August 1, 2022Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen
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Patent number: 11961800Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.Type: GrantFiled: July 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
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Patent number: 11955455Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.Type: GrantFiled: July 25, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh
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Patent number: 11956938Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.Type: GrantFiled: June 28, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
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Patent number: 11948839Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.Type: GrantFiled: November 1, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11948854Abstract: An electronic component includes a substrate, a functional portion, external connection conductor portions, and first and second heat-conducting portions. The functional portion is located on first principal surface of the substrate and portion generates heat during operation. The external connection conductor portions are located directly on the first principal surface of the substrate or located below the first principal surface without direct contact with the substrate. The second principal surface of the substrate includes first and second regions. When viewed in plan in a thickness direction of the substrate, the first region does not overlap the functional portion, and the second region coincides with the functional portion. The first heat-conducting portion is located directly on all or a portion of the first region or located over all or a portion of the first region without direct contact with the substrate.Type: GrantFiled: May 10, 2021Date of Patent: April 2, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Masato Nomiya
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Patent number: 11948895Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.Type: GrantFiled: July 4, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
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Patent number: 11950477Abstract: The present application discloses an OLED display panel, including a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the first-color subpixels, the second-color subpixels, and the third-color subpixels constitute a plurality of repeating units, the repeating units include a first repeating unit and a second repeating unit, and the first repeating unit and the second repeating unit are arranged at intervals in any row or any column.Type: GrantFiled: April 28, 2020Date of Patent: April 2, 2024Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Di Zhang
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Patent number: 11948975Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: GrantFiled: October 24, 2021Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 11942439Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.Type: GrantFiled: May 13, 2022Date of Patent: March 26, 2024Assignee: MediaTek Inc.Inventors: Tzu-Hung Lin, Yung-Chang Lien
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Patent number: 11942387Abstract: In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.Type: GrantFiled: September 30, 2021Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: John Carlo Cruz Molina, Julian Carlo Concepcion Barbadillo, Ray Fredric Solis De Asis
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Patent number: 11942385Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.Type: GrantFiled: March 29, 2022Date of Patent: March 26, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Yu Chen, Chang-Lin Yeh, Ming-Hung Chen
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Patent number: 11942408Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.Type: GrantFiled: May 20, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
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Patent number: 11932933Abstract: A semiconductor manufacturing device has a cooling pad with a plurality of movable pins. The cooling pad includes a fluid pathway and a plurality of springs disposed in the fluid pathway. Each of the plurality of springs is disposed under a respective movable pin. A substrate includes an electrical component disposed over a surface of the substrate. The substrate is disposed over the cooling pad with the electrical component oriented toward the cooling pad. A force is applied to the substrate to compress the springs. At least one of the movable pins contacts the substrate. A cooling fluid is disposed through the fluid pathway.Type: GrantFiled: July 25, 2022Date of Patent: March 19, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: OhHan Kim, HunTeak Lee, Sell Jung, HeeSoo Lee
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Patent number: 11923343Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.Type: GrantFiled: November 29, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyung Yoo, Jayeon Lee, Jae-eun Lee, Yeongkwon Ko, Jin-woo Park, Teak Hoon Lee
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Patent number: 11923342Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.Type: GrantFiled: March 28, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sanguk Han, Chajea Jo, Hyoeun Kim, Sunkyoung Seo
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Patent number: 11916031Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.Type: GrantFiled: May 16, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
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Patent number: 11915971Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.Type: GrantFiled: May 2, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang