Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: A display device including a base layer, a pixel circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulation layers, a first electrode electrically connected to the pixel circuit, a second electrode spaced apart from the first electrode, a light emitting element electrically connected to the first electrode and the second electrode, a first refraction layer disposed on the pixel circuit layer and having a first refractive index, and a second refraction layer disposed on the light emitting element and having a second refractive index larger than the first refractive index.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminals. The body includes: at least a diode structure configured to conduct a load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and drift and field stop regions of the same conductivity type. The cathode port includes first port sections and second port sections with dopants of the opposite conductivity type. A transition between each of the second port sections and the field stop region forms a respective pn-junction that extends along a first lateral direction. A lateral separation distance between immediately adjacent ones of second port sections in a second group is smaller than in a first group.

Abstract: Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.

Abstract: A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

Abstract: A radar chip package includes a radar monolithic microwave integrated circuit (MMIC) having a backside, a frontside arranged opposite to the backside, and lateral sides that extend between the backside and the frontside, wherein the radar MIMIC comprises a recess that extends from the backside at least partially towards the frontside; a plurality of electrical interfaces coupled to the frontside of the radar MIMIC; at least one antenna arranged at the frontside of the radar MIMIC; and a lens formed over the recess and the at least one antenna, wherein the lens is coupled to the backside of the radar MMIC.

Abstract: A method for manufacturing a semiconductor package structure is provided. The method includes: (a) providing a substrate, wherein an upper surface of the substrate includes a predetermined region and an energy-absorbing region adjacent to the predetermined region; (b) disposing a first device in the predetermined region of the upper surface of the substrate; and (c) bonding the first device to the substrate by irradiating an upper surface of the first device with an energy-beam, wherein a center of the energy-beam is moved toward the energy-absorbing region from a first position before bonding.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region; first nanowires formed over the first region of the semiconductor substrate; second nanowires with a diameter smaller than a diameter of the first nanowires formed over the second region of the semiconductor substrate; a first gate layer formed around the first nanowires; and a second gate layer formed around the second nanowires.

Abstract: A semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die includes at least one contact pad and a transistor including a first terminal formed within the active layer. A conduction path can include a plurality of first conduction path portions extending between the first terminal and the at least one contact pad and residing within a footprint of the at least one contact pad.

Abstract: A module is provided with a substrate including a principal surface, a plurality of electronic components arranged on the principal surface, a sealing resin covering the principal surface and the plurality of electronic components and including a trench between any of the plurality of electronic components, a ground electrode arranged on the principal surface, a conductive layer covering the sealing resin, and a magnetic member. The conductive layer is electrically connected to the ground electrode by a connecting conductor arranged so as to penetrate the sealing resin. The magnetic member includes a magnetic plate member arranged so as to cover the sealing resin and a magnetic wall member arranged in a wall shape in the trench. The connecting conductor and the magnetic wall member both fill the trench in a state of being formed in the trench.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.