Patents Examined by Long Pham
  • Patent number: 10593649
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Patent number: 10593688
    Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 17, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Scott A. Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela T. Hui
  • Patent number: 10593694
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Patent number: 10595409
    Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 17, 2020
    Assignee: INTEL CORPORATION
    Inventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
  • Patent number: 10586914
    Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 10, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Sajjad Amin Hassan, Mahendra Pakala, Jaesoo Ahn
  • Patent number: 10586773
    Abstract: Provided is a semiconductor device having a single inline package with high vibration resistance. External terminals (2a to 2c) are extracted from a resin encapsulation body (3) including a magnetic sensor and other semiconductor elements, a resin protruded portion is formed between the external terminal and the adjacent external terminal, and a gap is formed between the resin protruded portion and the external terminal. When the semiconductor device is mounted on a mounting substrate, the resin protruded portion is fixed on a surface of the mounting substrate, and the external terminal is bonded to a hole formed in the mounting substrate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: ABLIC INC.
    Inventor: Yasuhiro Taguchi
  • Patent number: 10586785
    Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: March 10, 2020
    Assignee: Invensas Corporation
    Inventors: Guilian Gao, Charles G. Woychik, Cyprian Emeka Uzoh, Liang Wang
  • Patent number: 10586805
    Abstract: According to one embodiment, a semiconductor memory device includes a first electrode layer having a first area, a second area, and a connection area connecting the first area to the second area, and a plurality of semiconductor pillars extending in a first direction through the first electrode layer in the first area and the second area. The plurality of semiconductor pillars are arranged in an array in a second direction and in a third direction intersecting with the second direction, the second direction and the third direction being parallel to the surface of the first electrode layer, and the connection area has no semiconductor pillars disposed therein.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Atsushi Konno
  • Patent number: 10586776
    Abstract: A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: ABLIC INC.
    Inventors: Yoichi Mimuro, Shinjiro Kato, Tetsuo Shioura
  • Patent number: 10580713
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
  • Patent number: 10573621
    Abstract: An imaging system using ultraviolet light or a manufacturing apparatus including the imaging system is provided. An imaging system includes an imaging element and a light source, which operates the imaging element with light that is emitted from the light source and reflected or transmitted by an object. A pixel included in the imaging element includes a photoelectric conversion element and a charge holding part. The light source has a function of emitting ultraviolet light to an object. The photoelectric conversion element is irradiated with the ultraviolet light reflected or transmitted by the object. The photoelectric conversion element has a function of changing the potential of the charge holding part when irradiated with the ultraviolet light and retaining the potential when not irradiated with the ultraviolet light.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akio Endo, Yusuke Yoshitani, Jun Koyama, Naoto Kusumoto
  • Patent number: 10559681
    Abstract: A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 10559513
    Abstract: A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 11, 2020
    Assignee: MEDIATEK INC.
    Inventor: You-Wei Lin
  • Patent number: 10559532
    Abstract: Certain aspects of the present disclosure generally relate to layout techniques for high-speed and low-power signal paths in integrated circuits with small channel devices. More specifically, according to certain aspects, an integrated circuit may comprise a plurality of layers, wherein at least a portion of the plurality of layers is configured to form a power/ground grid having odd-numbered metal layers and even-numbered metal layers, wherein a majority of traces of the even-numbered metal layers have a first orientation, and wherein a majority of traces of at least one of the odd-numbered metal layers are oriented parallel to the majority of the traces of the even-numbered metal layers; and one or more circuit components configured to use high-speed, low-power signals carried by one or more of the plurality of layers and to be powered by the power/ground grid.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Marina Salik, Anirban Banerjee, Elizabeth Deleev Hylander-Priebe
  • Patent number: 10553430
    Abstract: Technologies for inverting lithographic patterns are described. In some embodiments the technologies include a method for inverting a lithographic pattern of hole precursors, so as to form one or more high aspect ratio structures on or in a surface of a substrate.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Anthony A. St. Amour, Christopher P. Auth
  • Patent number: 10553561
    Abstract: A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound. The method further includes providing a second semiconductor die package; and bonding the conductive elements of the first semiconductor die package to contacts on the semiconductor die package.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Patent number: 10541304
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 10535793
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 14, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10535597
    Abstract: The present disclosure provides a semiconductor package device, which includes an interposer die. The interposer die includes a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 10529869
    Abstract: A connecting member includes a first part arranged between a first region of an electronic device and a board and a second part arranged between a second region of the electronic device and the board, a distance from an edge to the first part is longer than a distance from a center to the first part, and a distance from the edge to the second part is shorter than a distance from the center to the second part, a space is provided between the electronic device and the board and between the first part and the second part, and, in the board, a through hole communicating with the space is provided not to overlap with the center of the electronic device.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 7, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taiki Shitamichi, Takashi Miyake