Patents Examined by Long Pham
  • High voltage lateral junction diode device
    Patent number: 11322610
    Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar
  • Very thin embedded trace substrate-system in package (SIP)
    Patent number: 11309255
    Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
  • Self-aligned spacers for multi-gate devices and method of fabrication thereof
    Patent number: 11302825
    Abstract: A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Circuit board and packaged chip
    Patent number: 11296006
    Abstract: A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 5, 2022
    Assignee: MEDIATEK INC.
    Inventor: You-Wei Lin
  • Semiconductor package structure
    Patent number: 11289394
    Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Yu Chen, Chang-Lin Yeh, Ming-Hung Chen
  • Optimised fabrication methods for a structure to be assembled by hybridisation and a device comprising such a structure
    Patent number: 11289439
    Abstract: A method of fabrication of a semiconducting structure intended to be assembled to a second support by hybridisation. The semiconducting structure comprising an active layer comprising a nitrided semiconductor. The method comprises a step for the formation of at least one first and one second insert and during this step, a nickel layer is formed in contact with the support surface, and a localised physico-chemical etching step of the active layer, a part of the active layer comprising the active region being protected by the nickel layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 29, 2022
    Assignee: COMMISSARIAT ÂL'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventor: Jeannet Bernard
  • Semiconductor device packages and methods of manufacturing the same
    Patent number: 11289433
    Abstract: A semiconductor package structure includes a carrier, an antenna element, an electronic component, and a conductive structure. The antenna element, which includes an exposed portion, is disposed on the carrier. The conductive structure is disposed between the carrier and the exposed portion of the antenna element. The conductive structure electrically connects the electronic component to the carrier. The carrier, the exposed portion of the antenna element, and the conductive structure define an air space to accommodate the electronic component and to space the electronic component apart from the conductive structure.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, I Hung Wu
  • Package structure and method of manufacturing the same
    Patent number: 11282804
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Semiconductor device package including embedded conductive elements
    Patent number: 11282817
    Abstract: A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package. The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Organic photodetector with reduced dark current
    Patent number: 11283024
    Abstract: An organic photodetector comprising a first electrode, a second electrode, and a photosensitive organic layer between the electrodes, the photosensitive organic layer comprising a donor polymer and an acceptor compound, characterized in that the acceptor compound has a LUMO level shallower than that of the fullerene derivative PCBM.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: March 22, 2022
    Assignee: Cambridge Display Technology Limited
    Inventors: Gianluca Bovo, Nir Yaacobi-Gross
  • Manufacturing method of integrated circuit
    Patent number: 11276692
    Abstract: A method for manufacturing an integrated circuit is provided. The method includes forming first and second semiconductor fins; forming first and second dielectric fin sidewall structures on opposite sidewalls of the first semiconductor fin, wherein the first dielectric fin sidewall structure is higher than the second dielectric fin sidewall structure, and the second dielectric fin sidewall structure is between the first and second semiconductor fins; recessing at least a portion of the first semiconductor fin between the first and second dielectric fin sidewall structures until a top of the recessed portion of the first semiconductor fin is lower than a top of the first dielectric fin sidewall structure; and forming a first epitaxy structure on the recessed portion of the first semiconductor fin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok
  • Active-pixel sensor array
    Patent number: 11276725
    Abstract: An active pixel sensor is provided including a two-dimensional array of photodiodes arranged in at least two rows and a plurality of columns; a plurality of groups of photodiodes each having a floating diffusion region coupled thereto and being configured to receive electrons generated by photodiodes in the group; wherein the plurality of groups includes at least one first group disposed on a first row of the array, and at least one second group disposed on a second row of the array; and wherein the first group includes at least one photodiode on a first column and at least one photodiode on a second column, and the second group includes at least one photodiode on the second column and at least one photodiode on a third column.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 15, 2022
    Assignee: NewSight Imaging Ltd.
    Inventors: Eyal Yatskan, Eli Assoolin
  • Radio-frequency module
    Patent number: 11270922
    Abstract: A radio-frequency module 1a includes a wiring board 2, a first component 3a mounted on a lower surface 2a of the wiring board 2, a plurality of connection terminals 4, a first sealing resin layer 5 that covers the first component 3a and the connection terminals 4, a plurality of second components 3b mounted on an upper surface 2b of the wiring board 2, a second sealing resin layer 6 that covers the second components 3b, and a shield film 7. By adjusting surface roughness of a lower surface 5a of the first sealing resin layer 5, surface roughness of a lower surface 30a of the first component 3a, and surface roughness of a lower surface 4a of the connection terminal 4, it is possible to prevent abnormal deposition of plating and a crack in the first component 3a, and to prevent malfunction of the radio-frequency module 1a.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Takafumi Kusuyama, Yoshitaka Echikawa
  • Optoelectronic device
    Patent number: 11271135
    Abstract: An optoelectronic device comprising a semiconductor structure includes a p-type active region, an n-type active region, and an i-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell can comprise a layer of GaN and a layer of AlN. In some cases, a combined thickness of the layers comprising the unit cells in the i-type active region is thicker than a combined thickness of the unit cells in the n-type active region, and is thicker than a combined thickness of the unit cells in the p-type active region. The layers in the unit cells in each of the three regions can all have thicknesses that are less than or equal to a critical layer thickness required to maintain elastic strain.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: March 8, 2022
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Method of manufacturing connection structure of semiconductor chip and method of manufacturing semiconductor package
    Patent number: 11264339
    Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyujin Choi, Sunghoan Kim, Changeun Joo, Chilwoo Kwon, Youngkyu Lim, Sunguk Lee
  • Semiconductor devices, semiconductor device packages and method for manufacturing the same
    Patent number: 11264340
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Semiconductor device having metal interconnects with different thicknesses
    Patent number: 11264329
    Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Semiconductor package structure
    Patent number: 11264337
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 1, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • System and method to enhance reliability in connection with arrangements including circuits
    Patent number: 11264301
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • Method to enhance phosphor robustness and dispersability and resulting phosphors
    Patent number: 11261375
    Abstract: Briefly, in one aspect, the present invention relates to processes for producing a stabilized Mn4+ doped phosphor in solid form and a composition containing such doped phosphor. Such process may include combining a) a solution comprising at least one substance selected from the group consisting of: K2HPO4, an aluminum phosphate, oxalic acid, phosphoric acid, a surfactant, a chelating agent, or a combination thereof, with b) a Mn4+ doped phosphor of formula I in solid form, where formula I may be: Ax [MFy]:Mn4+. The process can further include isolating the stabilized Mn4+ doped phosphor in solid form. In formula I, A may be Li, Na, K, Rb, Cs, or a combination thereof. In formula I, M may be Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Y, La, Nb, Ta, Bi, Gd, or a combination thereof. In formula I, x is the absolute value of the charge of the [MFy] ion and y is 5, 6 or 7.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 1, 2022
    Assignee: General Electric Company
    Inventors: Matthew David Butts, James Edward Murphy, Mark Daniel Doherty