Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

Abstract: Provided are a method of producing an aluminate fluorescent material, an aluminate fluorescent material and a light emitting device. The production method includes heat-treating a mixture prepared by mixing a compound containing at least one alkaline earth metal element selected from the group consisting of Ba, Sr and Ca, a Mg-containing compound not acting as a flux, a Mn-containing compound, an Al-containing compound, a first flux containing at least one alkali metal element selected from the group consisting of Na, K, Rb and Cs, and a Mg-containing second flux to give an aluminate fluorescent material.

Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.

Abstract: The disclosure provides a semiconductor device having a separate active region and a method of fabricating the same. The semiconductor device includes a substrate, a plurality of isolation islands, a source region, and a drain region. The substrate includes a first active region, a second active region, and a plurality of separate active regions. The separate active regions are connected to the first active region and the second active region. The separate active regions and the isolation islands are alternately disposed. The gate structure includes a body portion and a plurality of extensions. The body portion disposed on a portion of the first active region. The extensions are coupled to the body portion and extend from the body portion to the isolation islands. The source region and the drain region are respectively located in the substrate in the first active region and the second active region.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: The present disclosure relates to a shielded integrated module, which includes a module substrate with a number of perimeter bond pads, at least one electronic component attached to the module substrate and encapsulated by a mold compound, a number of perimeter vertical shield contacts, and a shielding structure. The perimeter bond pads are surrounding the at least one electronic component and encapsulated by the mold compound. Each perimeter vertical shield contact is coupled to a corresponding perimeter bond pad and extends through the mold compound, such that a top tip of each perimeter vertical shield contact is exposed at a top surface of the mold compound. The shielding structure completely covers the top surface of the mold compound and is in contact with the perimeter vertical shield contacts.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract: In one example embodiment, a PCBA, an optoelectronic module, an electrical coupling, and/or a high speed interconnect may include a first contact pad, a second contact pad adjacent to and spaced apart from the first contact pad, a first wire coupled to the first contact pad via a first ball bump, and a second wire coupled to the second contact pad via a double ball bump.

Abstract: In an embodiment, a circuit arrangement is provided that includes a half-bridge circuit and a substrate having a major surface. The half-bridge circuit includes a high voltage node, a low voltage node and an output node. A high side switch and a low side switch are coupled in series and provide a pair and n pairs are coupled in parallel between the high voltage node and the low voltage node, n being an integer greater than or equal to 2. The output node is provided by an output connector on the major surface of the substrate. The output connector has an axis perpendicular to the major surface of the substrate and the n pairs are arranged on the major surface of the substrate and are uniformly distributed around the axis of the output connector.

Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

Abstract: According to certain aspects, a method for manufacturing packaged radio-frequency (RF) devices can include: providing a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side; mounting a first circuit on the first side of the packaging substrate; implementing a first overmold structure on the first side of the packaging substrate, the first overmold structure substantially encapsulating the first component; mounting a second component on the second side of the packaging substrate, the second component being located in an area of the second side where redundant ground pins may be located; implementing a set of through-mold connections on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins; forming a second overmold structure over the component and the set of through-mold connections; and removing a portion of the second overmold structure.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminals. The body includes: at least a diode structure configured to conduct a load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and drift and field stop regions of the same conductivity type. The cathode port includes first port sections and second port sections with dopants of the opposite conductivity type. A transition between each of the second port sections and the field stop region forms a respective pn-junction that extends along a first lateral direction. A diffusion voltage of a respective one of the pn-junctions in an extension direction perpendicular to the first lateral direction is greater than a lateral voltage drop laterally overlapping with the lateral extension of the respective pn-junction.

Abstract: A light emitting device package includes a mounting substrate including first and second lower electrode portions separated by a first groove, first and second upper electrode portions separated by a second groove connected to the first groove and disposed on the first and second lower electrode portions respectively, and an insulation support member filling the first groove, a light emitting device mounted on the first and second upper electrode portions of the mounting substrate, a double phosphor film covering an upper surface of the light emitting device, including a phosphor layer and a barrier layer sequentially stacked on each other, and having a thickness of 200 ?m or less, and a sealing member on the mounting substrate covering the light emitting device and the double phosphor film.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate, forming a gate structure including a metal gate on the substrate, forming an interlayer dielectric layer on the gate structure, forming a first contact hole extending through the interlayer dielectric layer to expose a surface of the metal gate, and removing a portion of the metal gate using a wet etching process to form a second contact hole having a cross-sectional size larger than a cross-sectional size of the first contact hole.

Abstract: A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalk from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalk. The lateral semiconductor nanotube shell comprises a hexagonal shape.

Abstract: The present invention discloses a modularized circuit for isolated circuit, wherein the isolated circuit includes at least two circuit components connecting in parallel and/or series, the circuit components, according to a circuit connection configuration, weld corresponding pins of the components directly, forming an integrated module in accordance with a desired connection method of the circuit, and saving circuit boards and wires; the circuit components are designed as a parallelepiped, and a plurality of bonding pads are arranged on part of an area on a surface of the parallelepiped. Due to constructing a circuit unit by welding connections in a way of building blocks, welding directly between components in a 3D space, comparing to the circuits limited in a circuit board plane as a PCB, it owns a wider design space.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.