Patents Examined by Long Pham
  • Multi-module integrated interposer and semiconductor device formed therefrom
    Patent number: 11257785
    Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang
  • Semiconductor device package and apparatus comprising the same
    Patent number: 11244936
    Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Hyeok Im, Hee Seok Lee, Taek Kyun Shin, Cha Jea Jo
  • Semiconductor package structures and methods of manufacturing the same
    Patent number: 11239178
    Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chanyuan Liu, Han-Chee Yen, Kuo-Hsien Liao, Alex Chi-Hong Chan, Christophe Zinck
  • Semiconductor device and method of producing semiconductor device
    Patent number: 11239144
    Abstract: A semiconductor device includes a mounting substrate; a first wiring electrode and a second wiring electrode disposed on a main surface of a mounting substrate; an interposing member disposed between the first wiring electrode and the second wiring electrode; a semiconductor element flip-chip connected with the first wiring electrode and the second wiring electrode via a first electrical connection member and a second electrical connection member so as to at least partially overlap the interposing member in a top surface view; and a resin disposed in contact with the semiconductor element and the mounting substrate. The wettability of the interposing member to the resin is higher than that of the mounting substrate to the resin. The resin is disposed in contact with the semiconductor element and the interposing member.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 1, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Hidesato Hisanaga, Akira Sengoku
  • Semiconductor device having a liner layer with a configured profile
    Patent number: 11217477
    Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joanna Chaw Yane Yin, Hua Feng Chen
  • Package structure and method of forming the same
    Patent number: 11217518
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a dielectric layer, a first redistribution layer (RDL) and a second RDL. The encapsulant laterally encapsulates the die. The dielectric layer is located on the encapsulant and the die. The first RDL penetrates through the dielectric layer to connect to the die. The second RDL is located on the first RDL and the dielectric layer. The second RDL and the first RDL share a common seed layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho
  • Display device
    Patent number: 11217624
    Abstract: A display device including a base layer, a pixel circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulation layers, a first electrode electrically connected to the pixel circuit, a second electrode spaced apart from the first electrode, a light emitting element electrically connected to the first electrode and the second electrode, a first refraction layer disposed on the pixel circuit layer and having a first refractive index, and a second refraction layer disposed on the light emitting element and having a second refractive index larger than the first refractive index.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woongsik Kim, Saehee Han
  • Interconnect structures of three-dimensional memory devices
    Patent number: 11205659
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The slit structure extends vertically through the memory stack. An upper end of the slit structure is above an upper end of the channel structure.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Hongbin Zhu, Juan Tang, Wei Xu
  • Semiconductor packages having package-on-package (PoP) structures
    Patent number: 11205640
    Abstract: Disclosed is a semiconductor package having a package-on-package (PoP) structure in which a signal region and a power region are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes an upper package substrate, a memory chip on the upper package substrate, a wire that electrically connects the memory chip to the upper package substrate, a power connector on the upper semiconductor package, a signal connector on the bottom surface of the upper package substrate, and an upper package molding material.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: December 21, 2021
    Inventor: Mingi Hong
  • Memory arrays and methods used in forming a memory array comprising strings of memory cells
    Patent number: 11205660
    Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manzar Siddik, Chris M. Carlson, Terry H. Kim, Kunal Shrotri, Srinath Venkatesan
  • Stack packages including an interconnection structure
    Patent number: 11205638
    Abstract: A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • High bandwidth module
    Patent number: 11201136
    Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
  • Deep trench isolation structure in semiconductor device
    Patent number: 11201082
    Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.
    Type: Grant
    Filed: November 16, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Methods and apparatus for wafer handling and processing
    Patent number: 11195740
    Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Kyle K. Kirby
  • Metal-oxide-semiconductor transistor and method of fabricating the same
    Patent number: 11195905
    Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Hua Hsu, Liang-An Huang, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Chih-Chung Wang, Kuang-Hsiu Chen, Ke-Feng Lin, Yan-Huei Li, Kai-Ting Hu
  • Ultra-small LED electrode assembly having improved luminance and method of manufacturing the same
    Patent number: 11195877
    Abstract: An ultra-small light-emitting diode (LED) electrode assembly having an improved luminance is provided. More particularly, an ultra-small LED electrode assembly in which light, which is blocked by an electrode and cannot be extracted, is minimized, an ultra-small LED device is connected to an ultra-small electrode without a defect such as an electrical short-circuit, and a very excellent luminance is exhibited even at a direct current (DC) driving voltage, and a method of manufacturing the same are provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 7, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yun Jae Eo, Yeon Goog Sung
  • Semiconductor device and method for fabricating the same
    Patent number: 11189695
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 30, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Radio-frequency module
    Patent number: 11183465
    Abstract: A radio-frequency module having high design flexibility of a shield with less likelihood of variation in shielding characteristics is provided. A radio-frequency module includes a multilayer circuit board, a component mounted on a top surface of the multilayer circuit board, and a plurality of metal pins having a bent shape such that both end portions can be connected to the top surface of the multilayer circuit board. Each of the plurality of metal pins is provided upright on the top surface of the multilayer circuit board in a state where both end portions are connected to the top surface of the multilayer circuit board, and is arranged near the component to make up a shield member.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo
  • Photo-sensitive silicon package embedding self-powered electronic system
    Patent number: 11177246
    Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Walter Hans Paul Schroen, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Method for fabricating image sensor
    Patent number: 11177305
    Abstract: A method includes depositing a first reflective layer over a substrate. A first dielectric layer is deposited over the first reflective layer. A second dielectric layer is deposited over the first dielectric layer. The second dielectric layer, the first dielectric layer, and the first reflective layer are etched to form a grid isolation structure that defines a recess. The recess is filled with a color filter.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Yin-Chieh Huang, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang