Abstract: Disclosed is a semiconductor package having a package-on-package (PoP) structure in which a signal region and a power region are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes an upper package substrate, a memory chip on the upper package substrate, a wire that electrically connects the memory chip to the upper package substrate, a power connector on the upper semiconductor package, a signal connector on the bottom surface of the upper package substrate, and an upper package molding material.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

Abstract: An ultra-small light-emitting diode (LED) electrode assembly having an improved luminance is provided. More particularly, an ultra-small LED electrode assembly in which light, which is blocked by an electrode and cannot be extracted, is minimized, an ultra-small LED device is connected to an ultra-small electrode without a defect such as an electrical short-circuit, and a very excellent luminance is exhibited even at a direct current (DC) driving voltage, and a method of manufacturing the same are provided.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: A radio-frequency module having high design flexibility of a shield with less likelihood of variation in shielding characteristics is provided. A radio-frequency module includes a multilayer circuit board, a component mounted on a top surface of the multilayer circuit board, and a plurality of metal pins having a bent shape such that both end portions can be connected to the top surface of the multilayer circuit board. Each of the plurality of metal pins is provided upright on the top surface of the multilayer circuit board in a state where both end portions are connected to the top surface of the multilayer circuit board, and is arranged near the component to make up a shield member.

Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Abstract: A method includes depositing a first reflective layer over a substrate. A first dielectric layer is deposited over the first reflective layer. A second dielectric layer is deposited over the first dielectric layer. The second dielectric layer, the first dielectric layer, and the first reflective layer are etched to form a grid isolation structure that defines a recess. The recess is filled with a color filter.

Abstract: Provided is a display device. The display device includes a base layer, a plurality of wavelength conversion parts disposed on one surface of the base layer, a partition wall disposed between the adjacent wavelength conversion parts of the plurality of wavelength conversion parts and having a first refractive index, a cover part configured to cover the plurality of wavelength conversion parts and having a second refractive index greater than the first refractive index, and an image display part disposed on a surface provided by the partition wall and the cover part.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: An electrode substrate for a transparent light emitting device display containing a transparent substrate; a wire electrode unit, which is provided on the transparent substrate and comprises a metal mesh pattern; and at least one light emitting device mounting unit provided on the transparent substrate, in which both an upper surface and a lateral surface of the metal mesh pattern of the wire electrode unit comprise a darkening layer pattern, and both an upper surface and a lateral surface of the light emitting device mounting unit do not comprise a darkening layer pattern.

Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Abstract: An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region and a second region; forming first nanowires over the first region of the semiconductor substrate; forming second nanowires with a diameter smaller than a diameter of the first nanowires over the second region of the semiconductor substrate; forming a first gate layer around the first nanowires; and forming a second gate layer around the second nanowires.

Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.