Patents Examined by Long Pham
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Patent number: 11587835Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.Type: GrantFiled: June 3, 2021Date of Patent: February 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
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Patent number: 11587946Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.Type: GrantFiled: September 14, 2020Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventor: Kang Sik Choi
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Patent number: 11587892Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.Type: GrantFiled: January 27, 2021Date of Patent: February 21, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Ko-Wei Chang
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Patent number: 11587852Abstract: An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.Type: GrantFiled: March 18, 2021Date of Patent: February 21, 2023Assignee: NXP USA, Inc.Inventors: Vikas Shilimkar, Ramanujam Srinidhi Embar
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Patent number: 11581266Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: GrantFiled: March 25, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongwan Kim, Kyong Hwan Koh, Juhyeon Oh, Yongkwan Lee
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Patent number: 11581360Abstract: A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a protrusion doping region in the protrusion. The pixel further includes a photosensitive device comprising a plurality of first regions, wherein each of the plurality of first regions is in the bulk and the protrusion.Type: GrantFiled: October 27, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bo-Tsung Tsai
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Patent number: 11574860Abstract: Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.Type: GrantFiled: January 22, 2021Date of Patent: February 7, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Takuya Goitsuka
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Patent number: 11572624Abstract: An apparatus for processing a substrate is provided. The apparatus comprises a processing chamber and a showerhead. The showerhead is in the processing chamber and has a plurality of first holes with a first size in a first zone of the showerhead, a plurality of second holes with a second hole size in a second zone of the showerhead, and a plurality of third holes with a third hole size in a third zone of the showerhead. The first hole size is different from the second hole size. The first zone is surrounded by the second zone. An area of the first zone is larger than an area of the second zone. The first hole size is different from the third hole size. The first zone is surrounded by the third zone, and an area of the first zone is larger than an area of the third zone.Type: GrantFiled: December 10, 2019Date of Patent: February 7, 2023Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventors: Chan-Sul Joo, Jee-Hoon Kim
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Patent number: 11572269Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.Type: GrantFiled: November 2, 2020Date of Patent: February 7, 2023Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
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Patent number: 11574880Abstract: The present disclosure relates to an electronic device with an integral filtering component. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.Type: GrantFiled: October 1, 2020Date of Patent: February 7, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Hsih-Yang Chiu, Ting-Cih Kang
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Patent number: 11569181Abstract: Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.Type: GrantFiled: December 5, 2020Date of Patent: January 31, 2023Assignee: International Business Machines CorporationInventors: Sushumna Iruvanti, Shidong Li, Steve Ostrander, Jon Alfred Casey, Brian Richard Sundlof
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Patent number: 11562930Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.Type: GrantFiled: October 1, 2020Date of Patent: January 24, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) CorporationInventor: Fei Zhou
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Patent number: 11557626Abstract: A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a floating diffusion node in the protrusion. The pixel further includes a gate structure over the bulk, wherein a top surface of the gate structure is above a top surface of the floating diffusion node. The pixel further includes a photosensitive device in the bulk. The pixel further includes an isolation well surrounding the photosensitive device.Type: GrantFiled: March 25, 2021Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bo-Tsung Tsai
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Patent number: 11557592Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.Type: GrantFiled: October 8, 2020Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Kamal M. Karda, Haitao Liu
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Patent number: 11551845Abstract: A multilayer coil component includes a multilayer body formed by stacking a plurality of insulating layers and including a coil built therein, and first and second outer electrodes electrically connected to the coil. The coil is formed by electrically connecting a plurality of coil conductors stacked together with the insulating layers. The multilayer coil component further includes, inside the multilayer body, first and second connecting conductors. The first connecting conductor connects between a portion of the first outer electrode covering the first end face, and a coil conductor facing the portion. The second connecting conductor connects between a portion of the second outer electrode covering the second end face, and a coil conductor facing the portion. Concerning the length direction, the first and second connecting conductors each have a length from about 2.5% to about 7.5% of the length of the multilayer body.Type: GrantFiled: March 29, 2019Date of Patent: January 10, 2023Assignee: Murata Manufacturing Co., Ltd.Inventor: Atsuo Hirukawa
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Patent number: 11541503Abstract: A polishing apparatus is a polishing apparatus polishing a target object formed on a surface of a film-shaped substrate. A polishing apparatus includes: a rotatable polishing tool acting on the target object; a slurry nozzle supplying a polishing slurry; and a polishing stage pressing the polishing tool against the target object. A surface of the polishing stage has an unevenness shape.Type: GrantFiled: March 23, 2020Date of Patent: January 3, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuji Yamamoto, Toru Furushige
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Patent number: 11545390Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.Type: GrantFiled: July 20, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Joanna Chaw Yane Yin, Hua Feng Chen
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Patent number: 11544437Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.Type: GrantFiled: December 2, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chih Hsieh, Chun-Fu Chen, Ting-Wei Chiang, Hui-Zhong Zhuang, Hsiang-Jen Tseng
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Patent number: 11538938Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.Type: GrantFiled: December 23, 2019Date of Patent: December 27, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
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Patent number: 11538792Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.Type: GrantFiled: January 4, 2021Date of Patent: December 27, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyung Yoo, Jayeon Lee, Jae-eun Lee, Yeongkwon Ko, Jin-woo Park, Teak Hoon Lee