Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

Abstract: In a substrate polishing apparatus where a polishing liquid passes through inside a rotary joint, the rotary joint requires maintenance. There is provided a substrate polishing apparatus that includes: a polishing head for holding a substrate; a rotary table that has a surface to which a first opening portion is provided; a polishing liquid discharge mechanism disposed to the rotary table; and a controller configured to control at least the polishing liquid discharge mechanism. The polishing liquid discharge mechanism includes a first cylinder, a first piston, and a driving mechanism that drives the first piston. The first opening portion is communicated with a liquid holding space defined by the first cylinder and the first piston. The controller controls the driving of the first piston by the driving mechanism to increase and decrease a volume of the liquid holding space.

Abstract: Provided is a method of double-side polishing a wafer by which variations of the GBIR values of polished wafers between batches can be reduced. In the method of double-side polishing a wafer, a current batch includes measuring the center thickness of the wafer before polishing (S100); setting a target GBIR value within a predetermined range (S110); calculating a polishing time of the current batch based on Formula (1) (S120); and polishing both surfaces of the wafer for the calculated polishing time (S130). Polishing time of current batch=polishing time of previous batch+A1×(center thickness of wafer before polishing in previous batch?center thickness of wafer before polishing in current batch)+A2×(GBIR value of wafer after polishing in previous batch?target GBIR value)+A3??(1), where A1, A2, and A3 are predetermined coefficients.

Abstract: A module (101) is provided with a substrate including a principal surface (1u), a plurality of electronic components (41, 42, and 43) arranged on the principal surface (1u), a sealing resin (3) covering the principal surface (1u), a ground electrode arranged on the principal surface (1u), a conductive layer (6) covering the sealing resin (3), and a magnetic member (5). The conductive layer (6) is electrically connected to the ground electrode by a plurality of connecting conductors (62) arranged so as to penetrate the sealing resin (3), and the magnetic member (5) includes a magnetic member plate-shaped portion arranged so as to cover the sealing resin (3) and a magnetic member wall-shaped portion (52) arranged in a wall shape in the sealing resin (3). The magnetic member wall-shaped portion (52) is longer than each of the connecting conductors (62).

Abstract: A polishing method capable of terminating polishing of a substrate, such as a wafer, at a preset polishing time is disclosed. The polishing method includes: polishing a substrate by pressing the substrate against a polishing surface of a polishing pad, while regulating a temperature of the polishing surface by a heat exchanger; calculating a target polishing rate required for an actual polishing time to coincide with a target polishing time, the actual polishing time being a time duration from start of polishing the substrate until a film thickness of the substrate reaches a target thickness; determining a target temperature of the polishing surface that can achieve the target polishing rate; and during polishing of the substrate, changing a temperature of the polishing surface to the target temperature by the heat exchanger.

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: A polishing pad useful in chemical mechanical polishing comprising a polishing portion having a top polishing surface and comprising a polishing material an opening through the polishing pad, and a transparent window within the opening in the polishing pad, the transparent window being secured to the polishing pad and being transparent to at least one of magnetic and optical signals, the transparent window having a thickness and a top surface having a plurality of elements separated by interconnected recesses to provide a pattern in the top surface that includes recesses for improved deflection into a cavity in the polishing pad during polishing.

Abstract: The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates.

Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.

Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.

Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

Abstract: An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.

Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.

Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Abstract: A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.