Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: Included are first and second inverters 1L, 1R, a first selection transistor N1 controlling a connection of an output terminal of the first inverter 1L to a bit line 11, and a second selection transistor N2 controlling a connection of an output terminal of the second inverter 1R to a bit line 12, wherein the first inverter 1L having a first load transistor P1 and a first drive transistor N3 and the second inverter 1R having a second load transistor P2 and a second drive transistor N4, function as a memory cell 1, and a ratio of a driving current quantity that can be outputted in an ON-state of the first drive transistor N3 to a driving current quantity that can be outputted in an ON-state of the first selection transistor N1, is larger than a first predetermined value.

Abstract: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

Abstract: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.

Abstract: A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The time interval during which the refresh device can be subsequently maintained in the refresh mode is next determined in relation to an energy requirement value obtained during the self-refresh mode and an energy capacity value from the associated energy source. The energy capacity value is preferably obtained by fully discharging the associated energy source. Preferably, the refresh device is characterized as a dynamic random access memory (DRAM), and the associated energy source is characterized as a rechargeable backup battery. A selected test pattern is preferably written to the refresh device and maintained thereby during the self-refresh mode.

Abstract: Provided is an internal voltage generator for a semiconductor memory includes: a first internal voltage drive device for driving an internal voltage in response to a first reference voltage corresponding to a target level of an internal voltage; and a second internal voltage drive device for driving the internal voltage in response to a second reference voltage having a lower level than the first reference voltage.

Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

Abstract: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Abstract: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

Abstract: A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause.