Abstract: An etching liquid contains iodine, an iodine compound and alcohol as solute, and solvent such as water. The etching liquid etches a gold or gold alloy layer formed on the surface of a substrate for a semiconductor device or a liquid crystal device evenly. A plurality of gold or gold alloy columns is formed on the layer. The columns are etched scarcely by the etching liquid. The etching liquid etches the gold or gold alloy layer existing between the columns evenly. The etching liquid may further contain a surfactant.

Abstract: Disclosed is a method for polishing a surface of a substrate containing Ru or a Ru compound in a surface region, said method comprising a polishing step with a polishing liquid containing tetravalent cerium ions. The polishing liquid is prepared by adding a compound having a tetravalent cerium ion or its solution to a solvent in or immediately before the polishing step of the substrate.

Abstract: A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. The stamp pattern may be formed on a substrate using semiconductor fabrication techniques. After the dielectric film is stamped, residual dielectric film is removed to allow access to an underlying layer. Via and trench regions formed within the dielectric film by stamping are then metalized to provide the high performance interconnections. Multiple layers of interconnections in the three dimensional structure are provided by stacking layers of stamped and metalized dielectric films on top of each other.

Abstract: A process for forming a lead-free bump on an electronic component includes preparing the electronic component with at least one bond pad and a passivation layer formed thereon; forming an under bump metallurgy (UBM) structure on the passivation layer and the bond pad; applying a photoresist over the passivation layer, the photoresist having at least one opening corresponding to the bond pad; depositing a thick copper layer (about 1 to 10 ?m thick) in the opening by electroplating; applying a copper-free or low-copper-content solder material on the copper layer; and performing a reflowing procedure under a suitable reflow temperature profile to allow copper ions to diffuse from the copper layer to the solder material so as to form the lead-free bump. This increases the copper content in the solder material but not raising the reflow temperature profile, thereby preventing deterioration of the photoresist due to over heat.

Abstract: A composition which includes liquid or supercritical carbon dioxide and an acid having a pKa of less than about 4. The composition is employed in a process of removing residue from a precision surface, such as a semiconductor sample, in which the precision surface is contacted with the composition under thermodynamic conditions consistent with the retention of the liquid or supercritical carbon dioxide in the liquid or supercritical state.

Abstract: In a formation method for forming a fine structure in a workpiece containing an etching control component, using an isotropic etching process, a mask having an opening is applied to the workpiece, and the workpiece is etched with an etching solution to thereby form a recess, corresponding to a shape of the opening, in a surface of the workpiece. The etching of the workpiece is stopped due to the etching control component eluted out of the workpiece in the etching solution within the recess during the isotropic etching process.

Abstract: The invention provides a chemical-mechanical polishing system comprising a polishing component, a surfactant, and a liquid carrier. The invention further provides a method of chemically-mechanically polishing a substrate with the polishing system.

Abstract: The present invention is directed to a CMP polishing slurry comprising cerium oxide particles, an organic compound having an acetylene bond (triple bond between carbon and carbon) and water, and a method for polishing a substrate which comprises a step of polishing a film to be polished of the substrate with the polishing slurry. In a CMP (chemical mechanical polishing) technique for flattening inter layer dielectrics, insulating films for shallow trench isolation and the like in a manufacturing process of semiconductor devices, the present invention enables the effective and high-speed polishing.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A CMP composition containing 5-aminotetrazole, e.g., in combination with oxidizing agent, chelating agent, abrasive and solvent. Such CMP composition advantageously is devoid of BTA, and is useful for polishing surfaces of copper elements on semiconductor substrates, without the occurrence of dishing or other adverse planarization deficiencies in the polished copper, even in the presence of substantial levels of copper ions, e.g., Cu2+, in the bulk CMP composition at the copper/CMP composition interface during CMP processing.

Abstract: A plasma etching is performed on a substrate having a pattern wherein an interval between neighboring openings formed on a resist mask is equal to or less than 200 nm, wherein the etching is performed by converting a processing gas comprising an active species generating gas which includes a compound having carbon and fluorine, and a nonreactive gas which includes xenon gas into a plasma. The nonreactive gas further includes argon gas.

Abstract: The polishing solution is useful for removing barrier materials in the presence of interconnect metals and dielectrics. The polishing solution comprises, by weight percent, 0.1 to 10 hydrogen peroxide, at least one pH adjusting agent selected from the group consisting of nitric acid, sulfuric acid, hydrochloric acid and phosphoric acid for adjusting a pH level of the polishing solution to less than 3, at least 0.0025 benzotriazole inhibitor for reducing removal rate of the interconnect metals, 0 to 10 surfactant, 0.01 to 10 colloidal silica having an average particle size of less than 50 nm and balance water and incidental impurities. The polishing solution has a tantalum nitride material to copper selectivity of at least 3 to 1 and a tantalum nitride to TEOS selectivity of at least 3 to 1.

Abstract: An additive composition for a slurry contains a first salt of polymeric acid including a first polymeric acid having a first weight average molecular weight and a first base material, and a second salt of polymeric acid including a second polymeric acid having a second weight average molecular weight and a second base material. A slurry composition is prepared by mixing the additive composition, a polishing particle composition, and water. When implementing a chemical mechanical polishing using the slurry composition, a favorable polishing selectivity is realized.

Abstract: A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.

Abstract: A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.

Abstract: A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for the etching process. The second stage etch is a reactive ion etch which directionally follows the facet profile to reach the target depth.

Abstract: The invention provides a polishing system and method of its use comprising (a) a liquid carrier, (b) a polymer having a degree of branching of about 50% or greater, and (c) a polishing pad, an abrasive, or a combination thereof.

Abstract: When plasma ashing is performed on a resist on a wafer, deposit gas containing at least one type of deposit component to be generated from a resist by ashing is added to a gas for plasma generation supplied from a gas supply system for plasma generation, by a deposit gas supply system. By this, the deposit component is actively deposited on the inner surface of a wafer processing chamber so as to protect the inner face of the wafer processing chamber from plasma. As a result, damage of the wafer processing chamber during ashing and particle generation due to the damage are prevented.