Abstract: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a hard mask so that portions of the hard mask are exposed over a portion of a cell region and over a portion of a periphery region, and then removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench having rounded corners is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, before the trench in the periphery region is deepened while a trench in the cell region is formed.

Abstract: This invention provides a polishing medium for CMP, comprising an oxidizing agent, a metal-oxide-dissolving agent, a protective-film-forming agent, a water-soluble polymer, and water, and a polishing method making use of this polishing medium. Also, it is preferable that the water-soluble polymer has a weight-average molecular weight of 500 or more and the polishing medium has a coefficient of kinetic friction of 0.25 or more, a Ubbelode's viscosity of from 0.95 mPa·s (0.95 cP) to 1.5 mPa·s (1.5 cP) and a point-of-inflection pressure of 5 kPa (50 gf/cm2).

Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mTorr.

Abstract: The present invention relates to a slurry for chemical mechanical polishing, which contains a silica polishing material, an oxidizing agent, a benzotriazole-based compound, a diketone and water.

Abstract: A post-etch residue cleaning composition for cleaning ashed or unashed aluminum/SiN/Si post-etch residue from small dimensions on semiconductor substrates. The cleaning composition contains supercritical CO2 (SCCO2), alcohol, fluoride source, an aluminum ion complexing agent and, optionally, corrosion inhibitor. Such cleaning composition overcomes the intrinsic deficiency of SCCO2 as a cleaning reagent, viz., the non-polar character of SCCO2 and its associated inability to solubilize species such as inorganic salts and polar organic compounds that are present in the post-etch residue and that must be removed from the semiconductor substrate for efficient cleaning. The cleaning composition enables damage-free, residue-free cleaning of substrates having ashed or unashed aluminum/SiN/Si post-etch residue thereon.

Abstract: A roll-off reducing agent comprising one or more compounds selected from the group consisting of carboxylic acids having 2 to 20 carbon atoms having either OH group or groups or SH group or groups, monocarboxylic acids having 1 to 20 carbon atoms, and dicarboxylic acids having 2 to 3 carbon atoms, and salts thereof; and a roll-off reducing agent composition comprising a roll off-reducing agent comprising one or more compounds selected from the group consisting of carboxylic acids having 2 to 20 carbon atoms having either OH group or groups or SH group or groups, monocarboxylic acids having 1 to 20 carbon atoms, and dicarboxylic acids having 2 to 3 carbon atoms, and salts thereof; an abrasive; and water.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A polishing composition comprising 0.03 to 0.5% by weight of an organic acid or a salt thereof, an abrasive and water, wherein the abrasive has a surface potential of from ?140 to 200 mV; a roll-off reducing agent comprising an inorganic compound having a property of controlling a surface potential of an abrasive in a polishing composition, wherein a surface potential of the abrasive in a standard polishing composition is controlled to ?110 to 250 mV by the presence of the inorganic compound, wherein the standard polishing composition is prepared which comprises 20 parts by weight of an abrasive, the abrasive being high-purity alumina having Al2O3 purity of 98.0% by weight or more composed of ?-type corundum crystal, 1 part by weight of citric acid, 78 parts by weight of water and 1 part by weight of an inorganic compound. The polishing composition or the roll-off reducing agent composition can be favorably used in polishing the substrate for precision parts.

Abstract: The present invention pertains to methods for removing unwanted material from a work piece. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer during semiconductor manufacturing. Methods involve implementing a hydrogen plasma operation with downstream mixing with an inert gas. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: CMP slurry contains a polishing component to polish a region to be polished, which includes at least one of a sub-region made of insulative material and a sub-region made of conductive material, and a restoring component to restore a scratch caused on the region to be polished. The scratch can be thus reduced during the polishing.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

Abstract: A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

Abstract: Aqueous polishing slurries for chemical-mechanical polishing are effective for polishing copper at high polish rates. The aqueous slurries according to the present invention may include soluble salts of molybdenum dissolved in an oxidizing agent and molybdic acid dissolved in an oxidizing agent. Methods for polishing copper by chemical-mechanical planarization include polishing copper with low pressures using a polishing pad and a aqueous slurries including soluble salts of molybdenum dissolved in an oxidizing agent and molybdic acid dissolved in an oxidizing agent, particles of MoO3 dissolved in an oxidizing agent, and particles of MoO2 dissolved in an oxidizing agent.

Abstract: The present invention provides a plasma etching method that can etch a metal film as a material to be etched selectively against an organic film underlying the material. The etching method comprising the steps of introducing an etching gas in an etching chamber wherein a material to be etched is placed, and exciting the etching gas to a plasma state to etch that material to be etched, wherein the material to be etched is a metal film 3 consisting of Au, Pt, Ag, Ti, TiN, TiO, Al, an aluminum alloy, or a laminated film of these films laminated on an organic film 5; and the etching gas is a mixed gas containing at least a gas selected from a group consisting of Cl2, BCl3, and HBr; and at least a gas selected from a group consisting of CH2Cl2, CH2Br2, CH3Cl, CH3Br, CH3F, and CH4.

Abstract: An SiO2 film layer formed at a wafer placed inside a process chamber of an etching device is etched by generating plasma from a process gas containing fluorocarbon which has been introduced into the process chamber. The contents of an etchant and the byproducts are measured through infrared laser absorption analysis. The individual contents thus measured are compared with the contents of the etchant and the byproducts in the plasma corresponding to the increase in the aspect ratio of a contact hole set in advance. The quantity of O2 added into the process gas is adjusted to match the measured contents with the predetermined contents. The quantity of O2 added into the process gas is continuously increased as the aspect ratio becomes higher. As a result, a contact hole is formed at the SiO2 film layer without damaging the photoresist film layer or inducing an etch stop.

Abstract: First, a lower film of AlNd Alloy and an upper film of MoW alloy are deposited in succession, and then patterned by an etchant including HNO3 of 0.1–10%, H3PO4 of 65–55%, CH3COOH of 5–20%, a stabilizer of 0.1–5% and the other ultra pure eater, to form a gate wire including a gate line, a gate electrode and a gate pad on a substrate. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in succession, and then, MoW alloy is deposited and patterned by an etchant including HNO3 of 0.1–10%, H3PO4 of 65–55%, CH3COOH of 5–20%, a stabilizer of 0.1–5% and the other ultra pure water, to form a data wire including a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Next, a passivation layer is deposited and patterned to form contact holes for exposing the drain electrode, the gate pad and the data pad, respectively.

Abstract: A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.

Abstract: Methods and apparatus for cleaning a semiconductor substrate that significantly reduce the number of particles falling onto the substrate during cleaning by coating all interior surfaces within a processing chamber with an adhesion film that has an increased sticking coefficient for any subsequently arriving etched species to promote a continuous film growth and improve adhesion of such etched species. Due to its increased sticking coefficient, this adhesion film reduces surface mobility of any arriving by-products to enable the growth of the continuous film of etched species. The continuous film of etched species adheres firmly to the adhesion film such that the etched species are prevented from flaking off and falling onto the substrate being cleaned. The methods and apparatus may clean a plurality of semiconductor substrates, whereby a plurality of adhesion films are sequentially deposited over a plurality of continuous film growths of removed materials for cleaning the substrates.