Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

Abstract: The present invention is directed to certain fluorinated surfactants, and use thereof in acid etch solutions, such as in aqueous buffered acid etch solutions. The etch solutions are used with a wide variety of substrates, for example, in the etching of silicon oxide-containing substrates.

Abstract: Disclosed herein is a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. By anodizing a metal core which is opened through a masking process, oxidation layers are formed in open areas of the metal core to insulate portions of circuit pattern from each other. Further, by electroplating portions provided between the oxidation layers with copper or filling conductive paste between the oxidation layers using a screen, a package substrate having a fine circuit pattern is achieved.

Abstract: Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photoresist in a conventional PR strip apparatus. In addition, the methods can shorten waiting time and maintain consistency in the process by performing the PR strip and cleaning at the same time in the same chamber. The resultant devices have lower via contact resistance and its deviation, as compared to the conventional PR strip and ACT wet cleaning.

Abstract: The present invention is related to a composition comprising an oxidizing compound and a complexing compound with the chemical formula wherein R1, R2, R3 and R4 are selected from the group consisting of H and any organic side chain. The oxidizing compound can be in the form of an aqueous solution. The complexing compound is for complexing metal ions. Metal ions can be present in the solution or in an external medium being contacted with the solution.

Abstract: A method of etching the trench portions of a thermal inkjet printhead using a robust mask that precisely defines the area of the substrate surface to be etched and that protects the adjacent drop generator components from damaging exposure to the silicon etchant. The process in accordance with the present invention uses as a mask some of the material that is also used in patterned layers for producing the drop generator components on the substrate. The placement of the mask components on the substrate occurs simultaneously with the production of the drop generator components, thereby minimizing the time and expense of creating the silicon-etchant mask.

Abstract: A method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d)calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations.

Abstract: A method for preventing the deterioration of an electrode caused by the build up of deposits in openings of the electrode. Gas is supplied to each of the openings in order to prevent deposits from adhering to the openings before or after the etching treatment.

Abstract: A method for fabricating a nitride semiconductor element according to the present invention comprises the steps of: forming a nitride semiconductor layer 13 on a base substrate 11; forming, on part of the upper surface of the nitride semiconductor layer 13, a conductive film 14 made of an electron emitting layer 14b and a dry etching mask layer 14a from bottom to top; performing dry etching on the nitride semiconductor layer 13; and performing wet etching on the nitride semiconductor layer 13 by emitting electrons from the nitride semiconductor layer 13 through the conductive film 14 to the outside.

Abstract: The present invention provides an aluminum etchant solution for etching an aluminum surface in the presence of solder bumps. The etchant solution includes about 42% to about 80% phosphoric acid; about 0.1% to about 6% nitric acid; about 5% to about 40% acetic acid; about 0.005% to about 5% of an amine oxide surfactant; about 0.1% to about 8% of a Pb solubilizing additive; and about 5 to about 25% de-ionized water; wherein the solder bumps are substantially phosphate free after the etching. Also provided is a process for etching an exposed aluminum surface in a semiconductor structure in the presence of solder bumps including the steps of: contacting the exposed aluminum surface with the etchant solution; rinsing the semiconductor structure with de-ionized water; and drying the semiconductor structure to remove residual water; wherein the solder bumps are substantially phosphate free after the etching.

Abstract: A composition and process for the precision polishing of substrates such as semi-conductor chips is disclosed. The composition and process make use of soluble or insoluble organic nitro compounds as oxidizers and/or abrasive particles. Nitrogen containing reduction products of the foregoing organic nitro compounds may also be included.

Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

Abstract: A cleaning solution for use in removing a damaged portion of a ferroelectric layer, and a cleaning method using the solution. The cleaning solution includes a fluoride, an organic acid with carboxyl group, an alkaline pH adjusting agent and water.

Abstract: A semiconductor device manufacturing method comprises forming a first insulating film including silicon, carbon, nitrogen, and hydrogen above a substrate in a first chamber, carrying the substrate into a second chamber other than the first chamber, and discharging a rare gas in the second chamber, and forming a second insulating film including silicon, carbon, oxygen, and hydrogen above the first insulating film after the discharging the rare gas.

Abstract: A polishing liquid composition is applicable as a means of forming embedded metal interconnections on a semiconductor substrate. In a surface to be polished comprising an insulating layer and a metal interconnection layer, the polishing liquid composition is capable of maintaining a polishing speed of the metal layer, of suppressing an etching speed, and of preventing dishing of the metal layer.

Abstract: A method for forming uniform, sharply defined periodic regions of reversed polarization within a unidirectionally polarized ferroelectric material proceeds as a two-step process. First, alignment keys are formed on upper and lower planar surfaces of a unidirectionally polarized ferroelectric material by producing a spaced pair of alignment key shaped domain reversed regions and etching alignment key shaped notches in the upper and lower surfaces where the domain reversed regions intersect the surface planes. These notches, being vertically aligned between the upper and lower surfaces, are then used to align photomasks over a surface coating of photoresist formed directly on the material surface or on SiO2 layers coating the material surface.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.

Abstract: Non-chromate solutions for treating and/or etching metals, particularly, aluminum, aluminum alloys, steel and titanium, and method of applying same wherein the solutions include either a titanate or titanium dioxide as a “drop-in replacement” for a chromium-containing compound in a metal surface etching solution that otherwise would contain chromium.

Abstract: A method of making a micro corner cube array includes the steps of: providing a substrate, at least a surface portion of which consists of cubic single crystals and which has a surface that is substantially parallel to {111} planes of the crystals; and dry-etching the surface of the substrate anisotropically with an etching gas that is reactive with the substrate, thereby forming a plurality of unit elements of the micro corner cube array on the surface of the substrate. Each of the unit elements is made up of a number of crystal planes that have been etched at a lower etch rate than the {111} planes of the crystals.