Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.

Abstract: One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

Abstract: In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A second non-conformal oxide is provided over the first non-conformal oxide. The second oxide is annealed in a boron-containing atmosphere, and the first oxide prevents boron diffusion from the second oxide into the gate and substrate. The second oxide may then serve as an etch stop, a CMP stop, or both.

Abstract: A wet etching system for selectively patterning substrates having regions covered with self-assembled monolayers (SAM) thereby controlling the etch profile. The system contains a) a liquid etching solution; and b) at least one additive to the liquid etching solution having a higher affinity to the regions of the substrate covered with the SAMs than to the other regions of the substrate. Also provided is a method of selectively patterning substrates having regions covered with self-assembled monolayers (SAMs), thereby controlling the etch profile, the method consisting of the steps of a) providing a liquid etching solution; b) adding at least one additive to said etching solution having a higher affinity to the regions of the substrate covered with the SAMs than to the other regions of the substrate; and c) etching said substrate with said liquid etching solution containing at least one additive.

Abstract: Disclosed herein is a method of manufacturing a FLOTOX type EEPROM. According to the method, the thickness of an oxide film in a tunneling implanted region is formed thicker than that of an oxide film in a peripheral active region by use of enhanced oxidation of the tunneling implanted region. Then, a tunnel window region and the peripheral active region are dry-etched simultaneously and an etching end point of the peripheral active region is detected. Thereafter, the oxide film that remains in the tunnel window region is removed by wet etching.

Abstract: A method for reducing wafer damage during an etching process is provided. In one of the many embodiments, the method includes assigning a bias voltage to each of at least one etching process, and generating the assigned bias voltage before initiation of one of the at least one etching process. The method further includes applying the assigned bias voltage to an electrostatic chuck before initiation of one of the at least one etching processes. The assigned bias voltage level reduces wafer arcing.

Abstract: A resist pattern is formed at an outermost peripheral end of the surface of a wafer. Thereafter, the back of the wafer is back-etched using chemicals to thin the wafer. A passivation film is left behind only at scribe lines for separating semiconductor chips located at the outermost peripheral end of the wafer surface and thereafter the wafer is back-etched.

Abstract: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition comprises an organometallic-modified colloidal abrasive and a nitrogen-containing polymer compound (e.g., a polyalkyleneimine, such as polyamidopolyethyleneimine). The composition possesses both high stability towards gelling and/or solids formation and high selectivity for metal removal in metal CMP. The composition may further comprise an oxidizing agent in which case the composition is particularly useful in conjunction with the associated method for metal CMP applications (e.g., copper CMP).

Abstract: A method for in-situ reduction of volatile residual contamination on a semiconductor process wafer following a plasma etching process including providing an ambient controlled chamber for accepting transfer of a semiconductor process wafer under controlled ambient conditions following a plasma etching process; providing a heat exchange surface disposed with the ambient controlled chamber in heat exchange relationship with means for heating the heat exchange surface; transferring a semiconductor process wafer having volatile residual contamination under controlled ambient conditions to the ambient controlled chamber; mounting the semiconductor process wafer in heat exchange relationship with the heat exchange surface; and, heating in-situ the heat exchange surface for a time period to thereby heat the semiconductor process wafer to vaporize the volatile residual contamination on the semiconductor process wafer while simultaneously removing a resulting vapor from the ambient controlled chamber.

Abstract: A method of manufacturing a semiconductor device includes a providing step and a polishing step. In the providing step, a semiconductor wafer is provided. The semiconductor wafer has a plane area including a plane surface and a peripheral area surrounding the plane area. The peripheral area has a hemispherical surface extending from the plane surface to a wafer end. The distance from an end of the plane surface to the wafer end is about 800–1000 ?m. In the polishing step, mechanically and chemically polishing is conducted using a polishing pad with a polishing slurry.

Abstract: The use of organic nitro compounds, such as nitrobenzene sulfonic acids, in chemical mechanical polishing compositions is disclosed. Chemical mechanical polishing slurries are widely used in polishing and planarizing silicon wafers and other fine surfaces. Inorganic nitro compounds are widely used in these slurries as oxidant sources. However, organic nitro compounds, particularly aromatic nitro compounds, are here suggested as advantageous substitutes.

Abstract: When an electronic device having an element including an insulating metal oxide film is manufactured, either dry cleaning or a cleaning solution containing substantially no water is used in a cleaning step conducted after a step of forming the insulating metal oxide film.

Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.

Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.

Abstract: The invention provides a method of polishing a substrate containing a low-k dielectric layer comprising (i) contacting the substrate with a chemical-mechanical polishing system comprising (a) an abrasive, a polishing pad, or a combination thereof, (b) an amphiphilic nonionic surfactant, and (c) a liquid carrier, and (ii) abrading at least a portion of the substrate to polish the substrate.

Abstract: A method of endpoint detection during plasma processing of a semiconductor wafer comprises processing a semiconductor wafer using a plasma, detecting radiation emission from the plasma during the semiconductor processing, and tracking data points representing changes in spectra of the radiation as a function of time during the semiconductor processing. At any point prior to or during processing a plurality of profiles are provided, each profile representing a different processing condition affecting detection of the desired plasma processing endpoint of the semiconductor wafer. After selecting a desired profile, a first set of parameters are input, representing simplified values for determining when changes in spectra of the radiation indicate that plasma processing of the semiconductor wafer reaches a desired endpoint.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.