Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

Abstract: A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.

Abstract: A system and method for balancing the capacitive charge on touch sensor electrodes so that every two adjacent routes have the same capacitance as any other adjacent two routes, wherein routing electrodes are spaced further and further apart, or graduated, as they get longer, to thereby balance the capacitance on the touch sensor electrodes without having to add or subtract an offset from each touch sensor electrode.

Abstract: A latch is analyzed to determine meta-stable voltage bias points, which are then used to determine one or more of a settling time of the latch, a mean time before failure (MTBF) for a synchronizing circuit using the latch, or a regeneration time constant (Tau). The latch is analyzed by decomposing the latch circuit into a feed-forward circuit and a feedback circuit and then determining a first transfer function for the feed-forward circuit and a second transfer function for the feedback circuit. The transfer functions are then used to solve for meta-stable voltage bias points. The meta-stable voltage bias points are used as an initial condition for a simulation or measurement of the latch in order to measure settling time. The voltage curve during the settling time of the latch is used to calculate a value for Tau.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.

Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

Abstract: A method for generating PCB inspection task data and inspecting a PCB is disclosed. The method by which Gerber data and CAD coordinate file generated at the time of PCB designing is matched to each other facilitates to generate a task data and allows a higher inspection accuracy. The task data generating method comprises generating a Gerber data comprising information for pads on the PCB, loading a CAD coordinate file comprising a coordinate of a component mounted on the pads, inferring a shape of lead and body of the component within a pad area by matching the Gerber data and CAD coordinate file, and then setting a pad area where a tip-end of the body locates as an inspection area.

Abstract: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first function corresponding to a first opcode combination, a subset of unused registers in the plurality of registers may be automatically determined. Further, clock gating logic may be automatically inserted into the design netlist, wherein the clock gating logic is operable to dynamically clock gate the subset of unused registers contemporaneously when the datapath executes the first function corresponding to the first opcode combination.

Abstract: The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected.

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining latency characteristics of the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, and retiming the configuration based on the second user input.