Abstract: The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization.

Abstract: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.

Abstract: An approach is provided in which a computing system retrieves a design description that corresponds to an electronic circuit design. The computing system selects an assertion corresponding to the electronic circuit design, which includes one or more assertion signal identifiers corresponding to one or more description signal points included in the design description. Next, the computing system creates a partitioned region from the design description based upon the description signal points. The computing system compiles and verifies the partitioned region that, in turn, verifies the electronic circuit design.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A computer identifies a metal layer, in a design, which contains routing track segregated by blockages. The sections of segregated routing track are removed and new routing track are added along the periphery of the blockage. It is determined if contact can be created between the component and the new routing track with the addition of a vertical interconnect access (VIA) structure. If contact can be created, then the VIA structures are added to create contact. If no contact can be created then another new routing track is added with (VIA) structures such that contact is created. Further routing track and VIA structures are added to higher metal layers to form a connection between a routing terminus located on a top metal layer and the new routing track and component.

Abstract: A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, and performing path rendering for the circuit design based on the positioning of the components. The method may also include sending an output file with the path rendering to a web browser.

Abstract: One method implementation disclosed includes detecting matching leaf cells that are functionally identical (optionally, functionally similar) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy.

Abstract: A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.

Abstract: A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.

Abstract: A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: The present invention aims to improve accuracy of a planar manufacturing drawing used to instruct manufacture of a three-dimensional structure in a planar form. According to path plan information is acquired by a path plan information acquisition unit 11a and manufacturing requirement information is acquired by a manufacturing requirement information acquisition unit, a layout configuration production unit 11c produces a layout configuration model in which the three-dimensional structure is laid out in a planar manner based on a manufacture layout and distortion of the wire harness. Then, a simulation unit 11d simulates a transformation from the layout configuration model to the mounting configuration model with which the three-dimensional structure is mounted to a mount object. Then, an evaluation item evaluating unit 11e evaluates a predetermined evaluation item by comparing the simulation result and the three-dimensional structure indicated by the path plan information.

Abstract: In a method of supporting a layout design, a net list of an integrated circuit is divided into net lists of clock domain circuit aggregations. A timing constraint is generated to each of the clock domain circuit aggregations. An arrangement order of the clock domain circuit aggregations is determined to satisfy the timing constraint. A layout of the integrated circuit is generated by carrying out arrangement and wiring of the clock domain circuit aggregations based on the arrangement order.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.

Abstract: An improved approach is described for allowing designers to identify and utilize suitable IP for an electronic design. An architecture is provided that includes an IP portal and/or chip estimator to identify suitable IP from a catalog of IP, which is integrated with a hosted design environment to use and test that IP for the user's specific electronic design. An authorization mechanism may be used to control access to the IP from the IP catalog. This approach greatly enhances the probability that IP suppliers will be successfully connected with the target consumers of those IP blocks.

Abstract: To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system.