Abstract: Techniques for compacting routing in lower level blocks to free routing resources for upper level blocks are disclosed. In some embodiments, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block is obtained. The specification includes an initial routing plan for the lower level block. Subsequently, a compacted routing plan for the lower level block using constrained routing resources comprising fewer routing tracks than the initial routing plan and resulting in at least one unused track as well as a routing plan for the upper level block using the at least one unused track are generated.

Abstract: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimization comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimization, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

Abstract: The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer, and a reference layer are determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer having a first signal trace disposed thereon and the reference layer. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts disposed inside the first keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof.

Abstract: Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent. Some implementations account for covariance, and use joint probability as the criteria for the effective x-sigma corner (e.g., as opposed to a unique sigma level of each individual metric). Analysis results for each metric can be transformed to metric distributions in a common distribution framework, and a correlation matrix can be calculated. The transformed metric distributions can be input to a joint probability distribution set to achieve a target joint sigma level. The joint probability distribution and correlation matrix values can be used to back-calculate scaled x-sigma corners for each metric distribution. Simulation of the device can be performed at one or more of the scaled x-sigma corners.

Abstract: An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts 32 (structural features) are provided within the circuit design so as to force allocation of functional contacts (structural features) of the matched devices into the same pattern layer thereby reducing inter-device variation in contact position and/or size.

Abstract: Embodiments of the invention place surface-mount such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, between BGA pads.

Abstract: A method can include generating a first set of sample values for input variables in accordance with a prescribed set of probability distributions, running a set of simulations on an electronic component based upon the first set of sample values, multiplying the standard deviations of the original distributions by a scaling factor ?, generating a second set of sample values for the input variables based on the probability distributions thus generated, and running a set of simulations on the electronic component based on this second set of sample values. The method can also include the generation of Q-Q plots based on the data from the first and second set of simulations and data from a truly normal distribution or the distribution obeyed by the independently varying input parameters; and the use of these plots for assessment of the robustness and functionality of the electronic component.

Abstract: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.

Abstract: A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further includes a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.

Abstract: A method of optical proximity correction (OPC) includes the following steps. First, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into a first sub-layout pattern and a second sub-layout pattern. Then, an OPC calculation based on a first OPC model is performed on the first sub-layout pattern so as to form a corrected first sub-layout pattern and an OPC calculation based on a second OPC model is performed on the second sub-layout pattern so as to form a corrected second sub-layout pattern. Afterward, the corrected first sub-layout pattern and the corrected second sub-layout pattern are output from the computer system into a photomask.

Abstract: A method is disclosed for structuring a function plan into function plan sections. The function plan includes function modules. Individual function modules are connected to at least one other function module of at least one function module connection. If the function plan exceeds the predefined area of the function plan section, a first determination of the arising function module external connections in an assignment of the individual function modules to the individual function plan sections occurs for each function plan variant, and the individual function modules are assigned to the function plan sections according to the function plan variant having the least possible number of function module external connections.

Abstract: A method includes receiving a layout file for a reticle used to pattern a first die location in a computing apparatus, the layout file defining a plurality of kerf features. A flare map calculation area for the first die location covering at least a portion of a kerf region surrounding the first die location is defined in the computing apparatus. Features in the layout file into the region corresponding to the flare map calculation area that are associated with the patterning of die locations neighboring the first die location are copied in the computing apparatus to generate a modified layout file. A flare map of the portion of the kerf region included in the flare map calculation area based on the modified layout file is calculated in the computing apparatus.

Abstract: A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.

Abstract: A method for process proximity correction may include obtaining a point spread function (PSF) from test patterns, the test patterns including an etching process performed thereon, generating a target layout with polygonal patterns, dividing the target layout into grid cells, generating a density map including long-range layout densities, each of the long-range layout densities being obtained from the polygonal patterns located within a corresponding one of the grid cells, performing a convolution of the long-range layout densities with the PSF to obtain long-range etch skews for the grid cells, and generating an etch bias model including short-range etch skews and the long-range etch skews, each of the short-range etch skews being obtained from a neighboring region of a target pattern selected from the polygonal patterns in each of the grid cells.

Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Abstract: A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the indicator function to obtain preliminary Fourier coefficients, and scaling the Fourier coefficients for the Fourier representation of the mask transmission function, where at least one of the steps is carried out using a computer device.

Abstract: A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process.

Abstract: Approaches for binning integrated circuits using timing are provided. A method includes performing a statistical timing analysis of a design. The method also includes identifying bin sub-spaces within a process space of the design. The method further includes determining a frequency limit for each said bin sub-space. The method additionally includes closing timing to the frequency limit for each said bin sub-space.

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining latency characteristics of the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, and retiming the configuration based on the second user input.

Abstract: In one aspect, a technique for performing signal activity extraction in an integrated circuit an integrated circuit is described. The integrated circuit includes multiple nodes. The technique includes compiling a design of the integrated circuit, estimating signal activities at the nodes, determining a node of interest from the nodes, and connecting a signal activity circuit to the node of interest. The determination of the node of interest and the connection of the signal activity circuit to the node of interest first compared to the remaining nodes of the integrated circuit improves efficiency in determining nodes of the integrated circuit at which signals can be analyzed first. Such signal activity extraction may involve power analysis and power optimization.