Abstract: In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into.

Abstract: A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A first shape is identified in a layout of the IC corresponding to the design as being apart by a first distance from a second shape. The first distance is a forbidden distance and at least equal to a minimum distance requirement of a lithography system. A determination is made that the first shape and the second shape are colored using a first color. The first shape is changed to a second color, such that even though the first distance is at least equal to the minimum distance requirement of the lithography system, the first and the second shapes are placed on different masks to print the design, thereby improving the printability of the design.

Abstract: A timing constraint generating support apparatus includes a propagation unit that propagates, through a wire connecting the logic circuits, timing constraints set for the logic circuits by using circuit information that represents information relating to the logic circuits and connection information that represents information of the wire, a determination unit that determines whether or not a plurality of timing constraints different from each other are propagated through the wire by the propagation unit, and an output unit that outputs information representing that the timing constraints propagated through the wire overlap each other in a case where the plurality of timing constraints different from each other are determined to be propagated through the wire by the determination unit.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

Abstract: There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

Abstract: Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.

Abstract: Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.

Abstract: A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: segmenting a plurality of the features into a plurality of polygons; determining the image log slope (ILS) value for each of the plurality of polygons; determining the polygon having the minimum ILS value, and defining a mask containing the polygon; convolving the defined mask with an eigen function of a transmission cross coefficient so as to generate an interference map, where the transmission cross coefficient defines the illumination system to be utilized to image the target pattern; and, assigning a phase to the polygon based on the value of the interference map at a location corresponding to the polygon, where the phase defines which exposure in said multi-exposure process the polygon is assigned.

Abstract: Obtaining a function by convoluting a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of a projection optical system and a pupil function of the projection optical system. Calculating a Fourier transformed function by Fourier transforming the product of the obtained function and a diffracted light distribution from a pattern on an object plane of the projection optical system. Producing data of the pattern of the mask based on the Fourier transformed function.

Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.

Abstract: In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.

Abstract: Computer-implemented techniques are disclosed for verifying functional independence of logic designs that make use of redundant representations. Initially, the design of a logic component is obtained. Two representations of the component are computed, one in redundant form and another in non-redundant form. A randomness factor based on a time-varying value is injected into the second representation. The value from the second form is then constrained to the context of the logic component within a digital system. It is then possible to analyze the component using the first deterministic representation and the constrained second representation. This analysis allows verification of the component with downstream logic.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern.

Abstract: Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner.

Abstract: An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.

Abstract: A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract: According to one general aspect, a method may include simulating a memory circuit, wherein the memory circuit is configured to store data. The method may also include receiving, by the simulated memory circuit, a memory access operation. The method may further include dynamically determining, in response to the memory access, if, based on a set of predefined criteria, the simulated memory circuit should generate a memory error as the result of the memory access. The method may also include, if the simulated memory circuit is to generate the memory error, generating the memory error as the result of the memory access.