Abstract: The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer.

Abstract: A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.

Abstract: A microelectronic assembly (10) includes a printed circuit board (12) that includes a substrate (14) having a die attach region (22) and a plurality of first bond pads (24) disposed and spaced apart at the die attach region (22). A channel (26) effective in improving fluid flow extends across the die attach region (22) apart from the first bond pads (24). An integrated circuit die (16) is mounted onto the printed circuit board (12) and includes a major face (28) facing the substrate (14) and spaced apart therefrom by a gap (30) and second bond pads (25) disposed on the major face (28) in a pattern such that each of the second bond pads (25) registers with a first bond pad (24). Solder bump interconnections (18) connect the first bond pads (24) to the second bond pads (25). Encapsulant (20) is disposed within the gap (30) and flows over the substrate (14) and the channel (26) to encapsulate the solder bump interconnections (18).

Abstract: A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Abstract: The resin sealing layer enclosing the device is biased to a low voltage by means of an anchoring structure formed close to high-voltage contact pads. The anchoring structure is formed by a metal region deposited on the surface of the device and contacting the resin layer, and by a deep region extending from the surface of the device, beneath the metal region, to the substrate. The electrical field in the resin layer is confined between the high-voltage pads and the anchoring structure and prevented from generating polarity inversions in the semiconductor material at the low-voltage contact pads or any other points at which the resin layer contacts the body of semiconductor material.

Abstract: A package for optical semiconductor device comprising a metallic frame having a side wall provided with an optical fiber-securing portion for securing an optical fiber to be introduced through the side wall, and a metallic bottom plate for mounting the optical semiconductor device thereon. The metallic frame is provided at a lower portion of the side wall thereof with securing parts for securing the package to a substrate, each securing part outwardly extending in a direction parallel with the metallic bottom plate. The level of bottom face of the metallic bottom plate is made lower than that of the bottom face of the securing parts. The securing parts are integrally formed with the metallic frame.

Abstract: An aluminum interconnection of the invention contains scandium as an impurity, so that the hardness of the interconnection in improved. Moreover, after a thin Al-Sc alloy film is formed, an annealing is performed 80 as to make the crystal grain larger than the width of the interconnection. The resulting Al interconnection has a high resistance against a stressmigration or electromigration, when a current stress in applied at a practical temperature in an LSI. This greatly contributes to the fabrication of a semiconductor device having a fine structure.

Abstract: An integrated circuit (IC) package (10), having an integrated circuit (11) and a connecting substrate (12) comprising an insulating film (13), one side of which carries conductors (14) and the other side of which carries balls (15) connected to the respective conductors by means of via holes (16) in the film. The balls (15) are fixed directly to said via holes, the base of which is formed by the respective conductors. The balls are preferably made of a remeltable material such as tin lead and the fixation can be made initially by an adhesive substance. The process for connecting two connecting substrates (12, 22) by means of balls (15), one of which substrates comprises a film (13), one side of which is provided with conductors (14) and the other side of which is provided with via holes (16), consists of fixing the balls directly to the conductors in the via holes by remelting the balls. The balls can be soldered or prefixed by an adhesive substance to connecting pads (23) of a board (22).

Abstract: The present invention relates to a lead frame for the formation of a frame structure of an integrated circuit, more particularly, to a lead frame, having a structure possessing excellent bondability, solder wettability, and Ag paste adhesion. A lead frame for a semiconductor device comprises a lead frame material; a Pd plating or a Pd alloy plating, provided on the lead frame material; and a layer as an uppermost layer formed of a Pd oxide and gold or silver. A process for producing a lead frame for a semiconductor device comprises the steps of: plating a lead frame material with Pd or a Pd alloy; flasing the surface of the Pd or Pd alloy plating with gold (Au); and heat-treating the plated lead frame material in the air to provide a thin Pd oxide layer in only a Pd portion on the surface of a diffusion layer formed of Pd and Au.

Abstract: A resin sealing type semiconductor device includes a semiconductor element having electrodes and a fixing surface, and a heat radiator for cooling the semiconductor element. The heat radiator includes a mounting surface on which the semiconductor element is mounted. A bonding layer is formed on the mounting surface between the semiconductor element and the heat radiator. The planar dimension of the bonding layer is smaller than that of the fixing surface of the semiconductor element. The semiconductor element adheres to the bonding layer through an adhesive layer. A resin package seals the semiconductor element, the heat radiator, and parts of leads and wires.

Abstract: A chip package includes a circuit board having a first surface with an inner die-attach region, an outer signal trace region and an intermediate utility region. Within the utility region are a number of traces for providing fixed electrical potentials to an integrated circuit die mounted within the die-attach region. In the preferred embodiment, the utility region includes a ring-like ground trace, a V.sub.DD trace and a segmented outer trace, with the segments of the segmented trace being connected to at least two fixed voltages for operating the integrated circuit die. Bond wires or leads of a leadframe include inner wire/lead ends connected to input/output pads of the die and include outer wire/lead ends connected to either a trace or trace segment in the utility region or a signal trace located in the outer signal trace region. The resulting chip package may be of the ball grid array type.

Abstract: A semiconductor device has an electrode interposed between an interlayer insulation film and a wire which is bonded thereto. A main component of the electrode is aluminum and the electrode contains fine-grained silicon in a concentration of 0.1 to 0.6 weight %. As a result, even if large ultrasonic power, a large load or the like is applied to the electrode when the wire is wire-bonded, damage such as the formation of a crack hardly generates at the interlayer insulation film. Therefore, the occurrence of defects due to the wire-bonding can be reduced.

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: A microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts.

Abstract: A stress relaxation layer is inserted between an electrode layer and an antireflection layer to relax a stress imparted from one of the electrode and antireflection layers to the other. A semiconductor device is provided which can suppress separation of the antireflection film during device fabrication processes and dispense with the process of etching and removing the antireflection film.

Abstract: Cooling of densely packaged semiconductor devices is achieved by microchannels which extract heat by forced convection and the use of fluid coolant located as close as possible to the heat source. The microchannels maximize heat sink surface area and provides improved heat transfer coefficients, thereby allowing a higher power density of semiconductor devices without increasing junction temperature or decreasing reliability. In its preferred embodiment, a plurality of microchannels are formed directly in the substrate portion of a silicon or silicon carbide chip or die mounted on a ground plane element of a circuit board and where a liquid coolant is fed to and from the microchannels through the ground plane. The microchannels comprise a plurality of closed-ended slots or grooves of generally rectangular cross section. Fabrication methods include deposition and etching, lift-off processing, micromachining and laser cutting techniques.

Abstract: An active layer of a field effect transistor disposed on an InP substrate (101) comprises at least an InAs layer (105) and two InGaAs layers (104, 106). The InGaAs layer (104) is In.sub.x Ga.sub.1-x As (wherein 0.55<x<1) and the InGaAs layer (106) is In.sub.y Ga.sub.1-y As (wherein 0.55<y<1). The active layer comprises, for example, In.sub.0.53 Ga.sub.0.47 As layer (103)/In.sub.0.8 Ga.sub.0.2 As layer (104)/InAs layer (105)/In.sub.0.8 Ga.sub.0.2 As layer (106)/In.sub.0.53 Ga.sub.0.47 As layer (107). Electrons which have been leached out of the InAs layer (105) are confined into the InGaAs layers (104, 106), and about 90% of the active electrons are accumulated in the layers (104, 105, 106) to achieve an excellent electron transport performance, so that an excellent high frequency characteristic can be obtained exhibiting a high cut-off frequency and an improved transconductance.

Abstract: A semiconductor device including a first wiring layer formed on a main surface of a semiconductor substrate, and a first insulating film layer having first and second contact holes which reach the main surface of the semiconductor substrate formed on the first wiring layer. A second wiring layer is formed on the first insulating film layer, and a first electric conductor, connected electrically to the semiconductor substrate, is formed in the first contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second electric conductor, electrically connecting the second wiring layer to the semiconductor substrate is formed in the second contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second insulating film layer is formed on the second wiring layer and has a third contact hole which reaches the first contact hole.

Abstract: It is an object of the present invention to fix a semiconductor substrate and a thermal compensating plate in the alloy-free structure. An insulation resin (23) for side wall protection fixed on the outer periphery of a semiconductor substrate (1) and a projection (6a) inside an insulation tube are bonded with an adhesive agent (24) to restrict movements of the semiconductor substrate (1) in the radial direction. A thermal compensating plate (3) and a main electrode (5) are normally positioned with each other by a screw pin (32). A fixing ring (30) having resin or metal such as aluminum or the like which fits to the outer peripheral side of the main electrode (4) and the outer peripheral side of the thermal compensating plate (2) and the edge part of the upper main surface thereof restricts movement of the thermal compensating plate (2) in the radial direction.

Abstract: The invention provides a wire-bonding type semiconductor device including, a semiconductor chip, a plurality sets of electrode pads formed on the semiconductor chip, each set including a power supply electrode, at least one signal electrode pad and a gland electrode pad arranged in this order, a mount on which the semiconductor chip is placed, the mount being formed with the same number of extensions as the number of the gland electrode pads, the extension acting as gland leads, the same number of power supply leads as the number of the power supply electrode pads, the same number of signal leads as the number of the signal electrode pads, the power supply leads, the signal leads and the projections acting as gland leads being arranged in this order, and metal wires for connecting each of the power supply electrode pads, signal electrode pads and gland electrode pads to the power supply leads, the signal leads and the extensions, respectively, the metal wires being disposed substantially in parallel with one