Abstract: A method for manufacturing a light receiving portion for a solid state image pickup device includes the steps of forming a well of a second impurity type on a substrate of a first impurity type, forming a channel stop within an upper surface of the well, forming a vertical CCD portion within the upper surface of the well, forming a gate insulating layer on the upper surface of the well, channel stop and the vertical CCD portion, forming a charge carrying gate electrode above the vertical CCD portion, forming a light receiving photo diode by ion-implanting impurities of the first impurity type, forming a first impurity layer on the light receiving photo diode by ion-implanting impurities of the second impurity type into a surface of the light receiving photo diode, removing a portion of the gate insulating layer above the light receiving photo diode, depositing an insulating layer containing impurities of the first impurity type on the gate insulating layer, the charge carrying gate electrode and the first imp

Abstract: A power semiconductor component includes a first chip having a vertical first transistor. A second chip with a second vertical transistor is mounted on the first chip in such a way that load paths of the two transistors are connected in series. The configuration can easily be expanded into a full bridge.

Abstract: A back irradiation type light-receiving device, on which light is incident from the back side with respect to a charge-reading section of a semiconductor thin plate, is provided with a reinforcement member on the charge-reading section side. Electric signals are fed in and out from the charge-reading section by way of a polysilicon lead having a short wiring length and a low-resistance aluminum lead which is formed, after the completion of all the steps requiring a high-temperature treatment, so as to be physically and electrically direct-connected to the polysilicon lead. Accordingly, a charge generated in response to the received light can be read out with a high efficiency, while enabling a high-speed operation.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels.

Abstract: A highly heat conductive heat sink comprising diamond particles yet eliminating heat distortion problems caused by the difference in thermal expansion with a semiconductor, and a manufacturing method thereof. Melting of an alloy (C), which comprises a metal (A) of at least one metal selected from the group consisting of Cu, Ag, Au, Al, Mg, and Zn; and a metal (B) of at least one metal selected from the group consisting of the groups 4a and 5a of the Periodic Table and chromium, around diamond particles forms on the surface thereof a metal carbide (B'), which enables the strong bonding between the diamond particles and the metal (A) and thus produces a highly heat conductive heat sink having a much higher thermal conductivity than the metal (A). This structure is attainable by either an infiltration method or sintering method.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: The present invention relates to a laminated chip bead element demonstrating noise absorption characteristics over a broad range in a high frequency range of GHz or higher. An insulating body is constituted of a material achieved by mixing ferrite powder and an insulating resin. At least one signal conductor is embedded in the insulating body. It is desirable that the insulating body includes a plurality of composite members.

Abstract: An integrated circuit device with a vertical via/contact is described. An insulating layer covers semiconductor device structures in and on a semiconductor substrate. A conducting layer overlies the insulating layer. An intermetal dielectric layer overlies the conducting layer. An aluminum layer overlies the intermetal dielectric layer and fills a via hole extending through the intermetal dielectric layer and through the conducting layer wherein the said via hole includes an undercutting of the intermetal dielectric layer and wherein the portion of the via hole undercutting the interlevel dielectric layer has vertical sidewalls. The via hole may extend either partially through the conducting layer or all the way through the conducting layer to the underlying insulating layer. This completes the integrated circuit device.

Abstract: An FET semiconductor device comprises a doped silicon semiconductor substrate having a surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the P-substrate. A P-well is formed within the N-well forming a twin well. Field oxide regions are formed on the surface of the substrate located above borders between the wells and regions of the substrate surrounding the wells. A gate electrode structure is formed over the P-well between the field oxide regions. A source region and a drain region are formed in the surface of the substrate. The source region and the drain region are self-aligned with the gate electrode structure with the source region and the drain region being spaced away from the field oxide regions by a gap of greater than or equal to about 0.7 .mu.m.

Abstract: In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Abstract: A semiconductor package has a controlling IC attached to a die pad using an epoxy molding compound (EMC) pad. The EMC pad is formed so as to be slightly larger than the controlling IC. EMC pads are cut from an EMC pad pattern which is formed from a predetermined number of EMC tablets. The EMC pad pattern is molded by heating and pressing the EMC tablets into a wafer shape having a thickness of approximately 0.3 mm and a diameter of approximately 100 mm. Such a thin EMC pad is capable of providing sufficient dielectric strength, and allows for manufacturing of semiconductor packages at lower cost. In addition, conventional equipment can be used to fabricate the semiconductor packages. The packages are flexible, and even a thin package is not easily broken.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.

Abstract: A high-reliability COG-type liquid crystal display device is produced with a high production yield without using a thermo-compression bonding process thereby preventing the connection of a liquid crystal driver IC from encountering a failure which would otherwise occur due to a high temperature in the thermo-compression bonding process. The liquid crystal display device comprises a pair of substrates (13, 14) facing each other via a liquid crystal, at least a liquid crystal driver IC (7) mounted on one substrate (13) by means of direct connection to the one substrate (13), and a plurality of semiconductor input terminals (21) formed on the substrate (13) so that signals are applied to the IC (7) via the semiconductor input terminals (21). The semiconductor input terminals (21) of the liquid crystal panel (8) are connected to semiconductor driving output terminals (6) of a portable telephone device or the like via an elastic connector (12).

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using "self-structured masks" and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.

Abstract: After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire. The second insulating film made of a substance different from the side wall is layered in a region including the wire, and a via hole for embedding the second contact is provided in the second insulating film under such an etching condition that the side wall is harder to etch, and therefore an end portion of the wire is not etched and an exposed area of an internal wall of the via hole can be reduced. It is possible to suppress deterioration gap-filling characteristics due to gas discharge from the second insulating film and achieve a contact of good shape. Thus, this structure avoids deterioration in imbedding characteristics that is caused by a deviation of alignment when the wire is interposed between a stacked via consisting of the first and second contacts.

Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.

Abstract: A semiconductor device comprises a dielectric substrate formed on a metal carrier, a semiconductor chip formed on the dielectric substrate and having a first electrode, a microstrip line formed on the dielectric substrate and having a second electrode to be connected to the first electrode, and wires, having different lengths, for connecting the first and second electrodes.

Abstract: There is provided an improved metallization stack structure so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity.

Abstract: A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.

Abstract: A semiconductor device such as a semiconductor dynamic sensor which is produced at an improved chip yield is provided. Etching wiring having a main line and a branch line is formed on a chip region via an intervening insulating film. The chip region contains an N-type reduced thickness region and is surrounded by a P-type chip isolating layer. The etching wiring is formed with a gap (an etching wiring gap) from other etching wiring members or circuit wiring formed on the chip region via an intervening insulating film. The etching wiring gap is greater than any of the gaps between members of the circuit wiring.