Abstract: A method for preparing a circuitized organic substrate for the subsequent deposition of an adhesive thereon is provided. The method comprises exposing the circuitized substrate to a plasma formed from a gas mixture comprising a fluorine-containing entity. Preferably, the gas mixture used to form the plasma also comprises oxygen. It has been determined that treatment of the circuitized substrate with a plasma formed from a gas mixture comprising at least 20% by volume of the fluorine-containing entity and, preferably, up to about 80% by volume of oxygen reduces the spread of an adhesive deposited on the surface of the organic substrate. It has also been determined that such treatment does not adversely affect the subsequent bonding of wires to the wire bond sites that are present on the surface of the substrate.

Abstract: In a semiconductor storage device, a capacitor section is connected with a drain region of a MOS transistor by means of a polysilicon plug. The capacitor section has a lower electrode, a ferroelectric thin film, and an upper electrode stacked in this order. A TiN barrier metal is placed between the lower electrode and the plug. The lower electrode has a lower film made of a platinum-rhodium alloy and an upper film made of a platinum-rhodium alloy oxide which is in contact with the ferroelectric thin film.

Abstract: A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied.

Abstract: The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: An integrated circuit which includes a first transistor device portion having an N+ doped region drain terminal in an N- well in a P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; and a second transistor device portion including an N+ doped region drain terminal in the P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; conductive means connecting the drain region of the first transistor device portion to a node to be discharged, a conductor connecting the gate of the first transistor device portion to a source of biasing potential equal to the source voltage used in a low voltage process, another conductor connecting the source of the second transistor device portion to a source of ground potential; and a third conductor for providing a source of positive input potential to the gate terminal of the se

Abstract: A photodiode which senses only .lambda.2 without WDM in optical communication systems containing two signals of different wavelengths .lambda.1 and .lambda.2. The photodiode has a filter layer whose band gap wavelength .lambda.g satisfies an inequality of .lambda.1<.lambda.g<.lambda.2 for annihilating .lambda.1. For vanishing tails of signals, the peripheral pn-junction is formed around the central pn-junction. In the case, an n-electrode is mounted on both the peripheral p-region and the peripheral n-region.

Abstract: The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped .alpha.-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped .alpha.-Si or HSG-Si into textured tunnel oxide.

Abstract: A MOSFET device protects the device from the short channel effect and decrease the resistance of a gate of the device. The MOSFET device includes a gate formed on a substrate and two source/drain regions. The source/drain regions are formed in the substrate at the sides of the gate. An oxide layer includes a first structure and a second structure. The first structure is at the side walls of the gate with the top of the first structure being lower than the top of the gate. The second structure is formed on the substrate and is connected to the first structure. A first spacer is formed on the second structure and beside the first structure. A second spacer is formed on the second structure and beside the first spacer. A self-aligned metal layer is formed on the gate, the first spacer, and over the substrate. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.

Abstract: In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.

Abstract: A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.

Abstract: A photodetector having improved responsivity includes first, second and third contact layers and first and second absorption layers. The first and second absorption layers are disposed on opposite sides of the first contact layer. The second contact layer is disposed on the first absorption layer and the third contact layer is disposed on the second absorption layer. The first contact layer has a first polarity. The second and third contact layers have a second polarity which is opposite the first polarity. Preferably, the first and second absorption layers are each made of a material having approximately equivalent electrical characteristics and the second and third contact layers are interconnected. Alternatively, one absorption layer is responsive to a first wavelength and another absorption layer is responsive to a second wavelength.

Abstract: A semiconductor device is formed with interconnections having reduced electric resistance. The semiconductor device comprises an upper wiring formed on an insulating film with a barrier metal therebetween, a conductive plug formed in a plugging space of the insulating film and electrically connected to the upper wiring at an opening of the plugging space, and a sidewall formed on a side surface of the upper wiring, the bottom of the sidewall covering the opening of the plugging space not covered by the upper wiring.

Abstract: A microelectromechanical (MEM) device includes a substrate and a flexible cantilever beam. The substrate has positioned thereon a first interconnection line separated by a first gap and a second interconnection line separated by a second gap parallel to the first interconnection line. The substrate also has positioned thereon a first and second primary control electrode wherein one of the first and second primary control electrodes is positioned on one side of one of the first and second interconnection lines and the other one is positioned on the other side of the other first and second interconnection lines. The flexible cantilever beam has a top surface and a bottom surface and a beam width slightly larger than the gap widths at the gaps. A flexible anchor is secured to the bottom surface of the beam at a center of the beam and attached to a center of the substrate so as to position the beam orthogonally to the first and second interconnection lines.

Abstract: On a semiconductor substrate, a first circuit and a second circuit are provided with a space therebetween. The first circuit and the second circuit are connected to each other by a fuse portion. In the middle of the fuse portion, a connecting portion is interposed, which is made of a material highly resistant to corrosion. Accordingly, an improved semiconductor device with a corrosion-resisting fuse portion is accomplished, which ensures the layout to be designed much more freely.

Abstract: An improved bonding system is provided in which a metal heat spreader is bonded to semiconductor chip. A two adhesive system is used in which a first adhesive demonstrates high bond strength with a second adhesive exhibits high thermal conductivity.

Abstract: A semiconductor device is provided with a wiring body including an insulating supporting substrate, and signal lines, power lines and ground lines printed on first and second surfaces of the insulating supporting substrate. The wiring body is mounted on a semiconductor chip, inside pads of the lines of the wiring body are connected with bonding pads on the semiconductor chip through first metal lines, and outside pads of the lines are connected with leads of a lead frame. Since the wiring body has a structure in which the lines are supported by the insulating supporting substrate, refined and various line patterns can be formed by using the wiring body, and an impedance matching function can also be attained. Thus, the invention provides a semiconductor device which can exhibit high noise resistance for a high frequency signal and a high operation speed and a wiring body to be disposed in a high frequency circuit.

Abstract: A radiation-sensitive transducer with a doped semiconductor sensor is to be constructed on a mounting plate such that it does not deform during temperature fluctuations. On the back side of the mounting plate, i.e., the side opposite the side on which the semiconductor sensor is mounted, an additional element having the same dimensions as the semiconductor sensor is attached opposite the semiconductor sensor. The additional element is composed of the same semiconductor material as of the semiconductor sensor, but is undoped. Due to the corresponding size and material of the semiconductor sensor and the additional element, they respectively produce equal but opposite forces acting on the mounting plate during temperature fluctuations, so no deformation occurs.

Abstract: Electrodes for electrically connecting to the outside are formed along one long side of a rectangular semiconductor chip 20. The electrodes are arranged in two rows, one of output terminals 21 and the other of input terminals 22 and power supply terminals 23, or are arranged in one row of the output terminals, input terminals and power supply terminals. Input protective resistors and static electricity protective diodes 28 for the input terminals are located outside the output terminals to be separated from the output system by at least the size of the output terminals. The external circuit connected to the output terminals 21 of the semiconductor device, for example the wiring 35 extending from the inner leads 33 of a tape carrier 29 are routed inside the electrodes toward the opposite long side of the semiconductor device, so that the wiring area overlaps the top of the semiconductor device in a plan view.

Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.