Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal.

Abstract: An interconnection system in a semiconductor device comprises a Ti.sub.2 N film having a lower resistivity and a higher thermal stability at a higher temperature compared to a TiN film. The Ti.sub.2 N film is formed by rapid thermal annealing of a TiN film and a Ti film consecutively formed on an insulator film. The rapid thermal treating is effected in a nitrogen ambient at a substrate temperature of 700 to 900.degree. C. for 30 to 120 seconds.

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell.

Abstract: A semiconductor device 10 enables efficient use of semiconductor wafer and higher productivity by splitting an electric circuit function into a plurality of semiconductor chip portions 12 and interconnecting the plurality of semiconductor chip portions 12 on a single carrier tape.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.

Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: The present invention is An electrical interconnection on a substrate and a method for forming an electrical interconnection on a substrate. The electrical interconnection in the present invention comprises a first metal layer, a first diffusion barrier layer on the first metal layer, a second metal layer on the first diffusion barrier layer, an organometallic layer on the second metal layer, and an electrical interconnect layer on the organometallic layer. The first diffusion barrier layer prevents diffusion of the first metal layer and the second metal layer therethrough. The organometallic layer is preferably formed by contacting the second metal layer with an organic material to form a organometallic layer. The organometallic layer chemically and physically protects the second metal layer, particularly by preventing the oxidation thereof.

Abstract: A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Abstract: Methods of forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells therein includes the steps of forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and then forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is then formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is then formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to thereby define a plurality of vertical IGBT cells.

Abstract: A highly integrated semiconductor device is made using a high precision manufacturing process having a comparatively small number of process steps. The device is substantially free of misalignment between structures formed with respect to openings formed in the middle of layers. An interlayer insulating film with an opening is formed on a first conductor, and a second conductor is deposited on the resultant structure. Part of the second conductor enters the opening, thereby producing a depression in the second conductor, which has a sharp-angled bottom situated at the horizontal center of the opening. A film made of, for example, a nitride is deposited on the second conductor to fill the depression. Thereafter, this film is removed such that part of it remains in the depression. Using the remaining film as a mask, the second conductor is removed to the same level as the interlayer insulting film.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: A semiconductor package which includes a package substrate and a semiconductor chip located on the package substrate have coefficients of thermal expansion which differs by a large margin. The semiconductor chip has beveled edges and an epoxy is provided which reduce stresses on the semiconductor chip when the package is being heated.

Abstract: A semiconductor device having a substrate with a first conductivity type. The substrate has a top substrate region that also has the first conductivity type. A first doped region, a second doped region and a third doped region are located in the top substrate region where the first and second doped regions have a second conductivity type opposite the first conductivity type while the third doped region has the first conductivity type and where the third doped region is between the first and second doped regions. A doped well region is also in the top substrate region and has the second conductivity type and has the second doped region and at least a portion of the third doped region located therein. A method of forming the device is also provided herein.

Abstract: A semiconductor device includes a protection circuit and a guard ring. The guard ring is formed between a MOS transistor of a semiconductor substrate and internal circuits, to cut off a leak current from the MOS transistor to the internal circuits. The guard ring includes a well region and a pair of heavily doped impurity regions for med spaced apart from each other on the surface of the well region. The pair of doped regions have mutually different conductivity types and have substantially equal voltages applied to have potentials with respect to the source of the MOS transistor.

Abstract: A light-receiving element includes a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type which is formed in a predetermined region on a surface of the semiconductor substrate of the first conductivity type; and at least one semiconductor region of the first conductivity type which is formed so as to extend from an upper surface of the first semiconductor layer of the second conductivity type to the surface of the semiconductor substrate of the first conductivity type, thereby dividing the first semiconductor layer of the second conductivity type into a plurality of semiconductor regions of the second conductivity type. In the light-receiving element, a specific resistance of the semiconductor substrate of the first conductivity type is set in a predetermined range such that a condition Xd.gtoreq.

Abstract: A circuit built-in light-receiving element includes a buried diffusion layer of the second conductivity type, a buried diffusion layer of the first conductivity type, an epitaxial layer of the second conductivity type, a diffusion layer of the first conductivity type, and a signal processing circuit element. The buried diffusion layer of the second conductivity type is formed in a first region on a substrate of the first conductivity type. The buried diffusion layer of the first conductivity type is selectively formed in the buried diffusion layer of the second conductivity type. The epitaxial layer of the second conductivity type is formed on the buried diffusion layer of the first conductivity type. The buried diffusion layer of the first conductivity type and the epitaxial layer of the second conductivity type constitute a light-receiving element.

Abstract: A capacitor with a high dielectric-constant dielectric and a thick lower electrode decreases the leakage current. The thick lower electrode is on an interlayer insulating layer. Typically, the interlayer insulating layer is formed on or over a semiconductor substrate. The lower electrode has a top face, a bottom face, and side faces. The bottom face of the lower electrode is adjacent to the interlayer insulating layer. An insulating cap or cover layer is on and contacts the top face of the lower electrode. The insulating cap or cover layer covers the top face of the lower electrode and uncovers the side faces of the lower electrode. A capacitor dielectric layer covers and contacts the side faces of the lower electrode and the insulating cap or cover layer. An upper electrode is on and contacts the capacitor dielectric layer. The capacitor dielectric layer is sandwiched by the upper and lower electrodes to thereby constitute a capacitor structure.

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition.