Abstract: A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.

Abstract: Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement.

Abstract: A FET type superconducting device comprises a substrate having a principal surface, a thin superconducting channel formed of an oxide superconductor layer over the principal surface of the substrate, a superconducting source region and a superconducting drain region formed of an oxide superconductor layer over the principal surface of the substrate at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode, wherein the superconducting device is isolated by a isolation layer directly formed on the principal surface of the substrate, the superconducting layer of the su

Abstract: The present invention intends to provide a radioactive rays detection semiconductor device comprises a substrate, an insulating layer formed on the substrate, p-type Si films formed on the insulating layer and equal in resistance value change rates due to temperature change and different in thickness so as to differ in the changes of the resistance values corresponding to the change of the total dose of the radioactive rays, an insulating film covering the p-type Si films, electrodes deposited in contact holes which are formed in the insulating film to reach both end of the p-type Si films, and Al wiring connecting the electrodes close to each other.

Abstract: The trench capacitors formed in a semiconductor wafer include trenches formed in said semiconductor substrate, first storage nodes includes doped ion regions and doped polysilicon structures, the doped regions are formed in a surface of the trenches. The doped polysilicon structures are formed on the walls of the trenches. An isolation structure is formed on said substrate between said trenches for isolation. A dielectric layer substantially covers the first storage nodes. A field plate is formed on the isolation structure and Second storage nodes is formed in the trenches and on the dielectric layer.

Abstract: An integrated circuit combination includes a second piggy-back small integrated circuit chip mounted on the carrier of a first integrated circuit chip. The combination can be mounted on a board without requiring board space for interconnecting the first and second chips. The lid of the first chip is cut away so that the second chip can be mounted to the first without increasing the height of the combination over the height of the first chip. The two chips preferably comprise an FPGA and a PROM for programming the FPGA. The combination increases security as well as reducing board space because it is difficult to read a bitstream being transmitted from the PROM to the FPGA when the PROM is directly mounted on the FPGA.

Abstract: A low cost means is described to semi-isolate the substrate regions of an integrated circuit occupied by a plurality of circuit types with separate power supply connections but with interconnecting signals. The separate power supply connections are made to minimize noise generated by one circuit from coupling into another circuit. One example of integrated circuits with a noise coupling issue are the so called "mixed signal" circuits in which the switching transient noise of digital circuits can interfere with the performance of on board analog circuits. Because of a common substrate, noise injected into the substrate by one circuit can affect the performance of another. This invention reduces the effect of substrate noise by providing an isolation zone around a given circuit type of an integrated circuit by removing the field implant in this zone and placing a deep implant of the same polarity type as substrate in the N channel transistor regions.

Abstract: A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A wired ceramic board has on a main surface of a ceramic substrate thereof a plurality of bonding pads each of which has a projection having a solderable outer surface and positioned inside an outer periphery of each bonding pad when observed in a plan view. To each bonding pad is bonded a solder ball by using solder which is lower in melting point than the solder ball. The ceramic board and a resinous printed board are placed one upon another in such a manner that their bonding pads are aligned with each other. The bonding pads are soldered together with low melting point solder. The projection of each bonding pad is embedded in or surrounded by a mass of low melting point solder and joined with the mass of solder to constitute an integral unit while serving as a core of the unit.

Abstract: A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.

Abstract: A multilayer micro circuit module, and the method of manufacturing same, comprises a number of green sheets of ceramic material which are sintered before any other fabrication steps are undertaken. The sintered sheets are then formed with registration holes and via, and an electrically conductive pattern formed of a noble metal or copper is deposited onto one or both major surfaces of each sintered sheets. The sintered sheets are stacked one on top of the other to form a stack whose exterior surface is coated with a sealing material such as solder or glass and then fired at a temperature less than the melting point of a metal forming the conductive patterns so that the interior of the stack including the conductive patterns is substantially isolated from contaminants.

Abstract: A semiconductor memory device comprises a matrix of memory cells, each having a transistor and a capacitor. A first electrode, a dielectric film and a second electrode are sequentially staked on a silicon monocrystalline substrate and epitaxially grown to form a capacitor having a multilayer structure. Then, an SOI layer is formed on the monocrystalline substrate carrying thereon the capacitor with an insulator film interposed therebetween. A source/drain diffusion layer is formed in the SOI layer and a gate electrode is formed to produce a MOS transistor. Either the source or the drain of the source/drain diffusion layer of the transistor is connected to the second electrode by way of the polysilicon layer in the contact hole running through the SOI layer and the insulator film layer.

Abstract: A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer.

Abstract: An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A semiconductor device including a semiconductor chip; a plurality of electrodes provided on a surface of the semiconductor chip; an insulative board which includes a plurality of conductive patterns, one end of each of the plurality of conductive patterns being protruded from a periphery of the insulative board so as to function as an outer terminal; a connecting element for electrically connecting the outer terminal to a corresponding one of the plurality of electrodes; and a conductive element which is in electrical contact with a corresponding one of the plurality of conductive patterns.

Abstract: A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two metal layers in the semiconductor device forming a pair of plug to metal layer interfaces. A conductive trace is formed in an inter-metal dielectric layer between the metal layers, where the conductive trace couples the conductive plug to a pair of externally accessible pads. Each of the metal layers has a pair of pads. Using the pads coupled to the conductive trace, current is forced through each of the plug to metal interfaces and a voltage difference across each interface is measured in order to obtain the resistance of each interface. The total resistance of the inter-layer contact plug is similarly obtained and the resistance of the plug itself is obtained by subtracting the resistance of the two interfaces from the total resistance.

Abstract: A first polycide lead, which is formed on a silicon substrate, consists of a first doped polysilicon layer and a first tungsten silicide layer that is formed on the first doped polysilicon layer. An interlayer insulating film, which is formed on the silicon substrate, has an opening that reaches the first doped polysilicon layer. A second polycide lead, which is formed on the interlayer insulating film, consists of a second doped polysilicon layer that is connected to the first polycide lead in the opening and a second tungsten silicide layer that is formed on the second doped polysilicon layer. In the opening, the first and second doped polysilicon layers are in contact with each other at the side surfaces of the first polycide lead.

Abstract: An electronic module for data carriers having at least one integrated circuit includes an electrically conductive layer with contact surfaces for communication of the circuit with external devices and having an insulated layer which is connected to the conductive layer and has recesses for electrically connecting the contact surfaces with the circuit. Each recess protrudes partly into the contact surface adjacent the recess. The recesses may be formed in such a way that the area of insulating layer remaining in the center of the module takes up substantially only the integrated circuit surface.