Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: Packaging of high resolution linear solid state image sensors can result in a significant cost savings over conventional packaging processes, while adding several features. Cost reduction is accomplished by drastically reducing the cover glass size, eliminating the need for rounded corners as well as need for an epoxy ring on the cover glass, and integrating a wire bond light shield into the IC package. Additional cost savings are realized by eliminating the thermal cure cycle presently required to attach the cover glass, a process which can take several hours to completed. The invention replaces the conventional IC package with a two piece assembly. The bottom piece is a low profile plastic or ceramic IC package and the top piece is an inexpensive molded piece which serves as a cap with an integrated light shield aperture and cover glass holder.

Abstract: A UMOS semiconductor device has a surge absorbing structure around a drain lead region. A surge absorbing region such as an anode region or a region forming a punch-through or reach-through structure is formed near the drain lead region, and surrounded by a source region or source regions. The surge absorbing region forms a diode such as a zener diode with a highly doped buried layer or a drain region. With the diode, the surge absorbing structure controls the electric field around the drain lead region and thereby protects the gate insulating film from being damaged by a drain surge.

Abstract: An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

Abstract: The present invention includes forming word lines on a substrate. Next, nitride spacers are formed on the side walls of the word lines. In the cell area, a photoresist is patterned on the substrate to cover a coding region. Then, an ion implantation with n type conductive dopant is carried out to form buried bit lines in the cell area and in the peripheral area adjacent to the word lines. Afterwards, the photoresist is stripped. A high temperature thermal oxidation is then performed to activate the dopant and to form thick oxide structures to isolate the adjacent buried bit lines.

Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

Abstract: In a semiconductor device of the insulated gate type, a side wall silicon oxide layer of a desired width is formed on each side wall of a gate electrode and a silicon oxide layer to reduce a distance between the contact end of a source electrode with an N.sup.+ -type source region and the internal end of the gate electrode thereby to decrease the on-resistance even if the impurity concentration of the N.sup.+ -type is determined to be low. Since the impurity concentration of the N.sup.+ -type source region is lower than that of a P.sup.+ -type body region and higher than the surface impurity concentration of a P-type body region, the base width of a parasitic bipolar transistor related to the P-type body region is maintained in a proper value without increasing the depth of the N.sup.+ -type source region in excess.

Abstract: Arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously reducing the height of the floating gates in particular locations. The reduced height floating gate's topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: An integrated circuit inverted thin film resistor structure and method of manufacture having interconnect defining resistor contacts and leads resident within and coplanar with a supporting layer, resistive material uniformly overlaying the supporting layer and contacts, the resistive material diffused into the resistor/interconnect contact region.

Abstract: The present invention relates to semiconductor devices packaged using overcasting. The overcast devices of the present invention incorporate encapsulative materials, such as ultraviolet-curing material, which are cast in open stencils at approximately ambient pressure (and potentially at approximately ambient temperature) over electronic components mechanically and electrically connected to the substrate. The overcast semiconductor devices of the present invention may incorporate new encapsulative materials, including UV-cured materials and longer shelf life materials, poorly suited for the pressures and temperatures of injection molding. The overcast devices also allow the incorporation of substrate materials which are not feasible for use with a higher pressure, higher temperature forming process.

Abstract: A method for selective conductivity etching of a silicon carbide (SiC) semiconductor includes forming a p-type SiC layer on a substrate layer, forming an n-type SiC layer on the p-type SiC layer, and photoelectrochemically etching selected portions of the n-type SiC layer by applying a bias voltage to the n-type SiC layer in a hydrofluoric acid (HF) solution while exposing the layer to a pattern of UV light. The bias potential is selected so that the n-type SiC layer will photo-corrode and the p-type SiC layer will be inert and act as an etch stop. The light pattern exposure of the n-type SiC layer may be done by applying a photolithographic mask to the layer, by projecting a collimated light beam through a patterned mask, or by scanning with a focused micrometer-sized laser beam on the semiconductor surface.

Abstract: A method for preventing bonding pads from peeling caused by plug process comprises the following steps. First, a substrate is prepared, and then a first conductor is formed on the substrate. Next, a dielectric layer is formed on the first conductor. After that, a big contact window and a plurality of small contact windows are formed on the dielectric layer, wherein the plurality of small contact windows are located around the big window, and the sizes of the big contact window and small contact windows are over 3 .mu.m. Subsequently, a metal plug layer is formed on the dielectric layer, big contact window and small contact windows. Thereafter, the metal plug layer is etched back to form metal spacers on the sidewalls of the big contact window and small contact windows. Finally, a second conductor is formed on the dielectric layer, big contact window, small contact windows and metal spacers.

Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are butted together to save space. The bonding pads for the lower IC chip or chips are placed along the edges not butted with one another. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be placed at the top of the IC chips away from the ball grid array.

Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: An acoustical-electronic component operating with acoustical surface waves, includes a piezoelectric substrate in which an acoustical surface wave is guided and enters into interaction with an electron system disposed on the substrate in the travel path of the acoustical surface wave. The electron system is constructed as an electron channel that is tunable in its electrical conductivity by field effect. A tunable delay line, a resonator and a semiconductor sensor use the component.

Abstract: A multi-layered conductive device is constituted of a plurality of conductive elements disposed in at least two layers, and an insulating film disposed between the respective conductive elements. The multi-layered conductive device may be manufactured by forming a single conductive element, adhering an insulating film to at least one surface of the conductive element, cutting the conductive element to form at least two conductive strips, laminating at least two layers of conducting elements to from a single assembly and fixing the assembly with a resin.

Abstract: A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.

Abstract: A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

Abstract: An integrated circuit package which contains an integrated circuit. The internal integrated circuit is coupled to external lands located on a first outer surface of the package by a plurality of vias. The vias extend through the package from the first outer surface to an opposite second outer surface. The package has a plurality of devices such as capacitors that are mounted to the second outer surface. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.