Abstract: There is provided a semiconductor device including a semiconductor pellet having a plurality of bump electrodes on a surface thereof, a wiring board having a plurality of pad electrodes on a surface thereof, each one of the pad electrodes being engaged to an associated one of the bump electrodes when the wiring board is coupled to the semiconductor pellet, and a resin layer sandwiched between the semiconductor pellet and the wiring board for connecting them with each other therethrough, each of the bump electrodes being formed with one of a projection and a recess into which the projection is able to be fit, and each of the pad electrodes being formed with the other. For instance, the bump electrodes are formed by compressing a molten ball formed at a tip end of a gold wire onto the semiconductor pellet, and the projection is formed on the bump electrodes by cutting the gold wire so that a tip end portion of the gold wire leaves on the bump electrodes.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.

Abstract: A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Abstract: A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area structures to dampen or eliminate the intense electric field which would be generated at the corners of the conductive structures during the operation of the memory cell capacitor had the caps not been present.

Abstract: A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

Abstract: A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.

Abstract: A semiconductor device includes a semiconductor substrate having a first and a second region, a first wiring layer including a lower layer having polycrystal silicon portions including impurities at a high concentration and formed over the first region of the semiconductor substrate via an insulating film. An upper layer of the first wiring layer is a metal silicide having a first film thickness. A second wiring layer includes a lower layer formed over the second region of the semiconductor substrate via an insulating film and is formed of either a non-doped polycrystal portion or a polycrystal silicon portion having a resistivity of at least 10 &OHgr;cm. An upper layer of the second wiring layer is a metal silicide portion having a second film thickness thicker than the first film thickness.

Abstract: A container capacitor and method having an internal concentric fin. In one embodiment, the finned capacitor is a stacked container capacitor in a dynamic random access memory circuit. The finned container capacitor provides a high storage capacitance without increasing the size of the cell. The capacitor fabrication requires only two depositions, a spacer etch and a wet etch step in addition to conventional container capacitor fabrication steps.

Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.

Abstract: An image forming system utilizing a light emitting diode (LED array) having LEDs arranged along a curved line. The LEDs are either edge emitting type LEDs or surface emitting type LEDs. The LEDs of the LED array emit light towards a center or optical axis of the lens. A plurality of lenses are connected together to form a lens array. Alternatively, two lens arrays can be utilized. If two lens arrays are utilized, each of the lenses in the lens array includes an aspherical surface. The curved LED array prevents the flaring of light and produces an even pattern of light emission on a light receiving surface such as a photoconductive drum.

Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: An ohmic electrode structure includes an n-InxGa1−xAs layer where 0<x≦1; a Pt or Pd layer provided on the n-InxGa1−xAs layer; and at least one metal layer provided on the Pt or Pd layer. A semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.

Abstract: A storage node to be a lower electrode of a capacitor is electrically connected to a polysilicon columnar conductive body filling a contact hole with a second polysilicon film therebetween. The second polysilicon film covers the inside of an opening portion formed in the first polysilicon film. The polysilicon film columnar conductive body is electrically connected to a source/drain region of an MOS transistor at a contact. Thus, a semiconductor device with good electrical connection between the capacitor and the transistor may be provided.

Abstract: A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type.

Abstract: A buried sense electrode (8) having the same structure as that of a buried gate electrode (7) is provided in an n− layer (3) of an IGBT with a sense oxide film (10) interposed therebetween. The buried sense electrode (8) senses an electric potential of the n− layer (3). If an electric potential sensed by the buried sense electrode (8) is increased to exceed a gate threshold voltage of a MOSFET (21) having an n+ drain region (22), a p well region (23) and an n+ source region (24), the MOSFET (21) is turned ON. At this time, a gate voltage applied across a gate electrode (13) and an emitter electrode (11) of the IGBT is reduced to a value obtained by a sum of an ON-state voltage of the MOSFET (21), a breakdown voltage of a Zener diode (16) having an n+ cathode region (17) and a p+ anode region (18), and a forward voltage of a diode (19) having the p+ anode region (18) and an n+ cathode region (20).

Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.

Abstract: An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analogue device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.