Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in t

Abstract: In a chip type resistor, a middle coat which is a component of a cover coat has extensions or enclaves formed at portions on a surface of main upper electrodes of terminal electrodes. Auxiliary upper electrodes of terminal electrodes are formed extending over both the surface of extensions or enclaves of middle coat and the surface of main upper electrodes. Therefore, the step between the surface of terminal electrodes at opposing ends of resistive film and the surface of cover coat for the resistive film can be reduced or eliminated with low cost.

Abstract: Si.sub.3 N.sub.4 having high humidity resistance is used as a surface protecting insulating film covering a metal layer. At a bonding pad portion where metal layer is directly exposed, coverage is provided by anti-corrosion metal portion consisting of a titanium-tungsten alloy layer and gold layers. At a signal processing circuit portion, light intercepting structure and interconnection are provided similarly by titanium-tungsten alloy layer and gold layer. Thus humidity resistance of a photodetector element containing a circuit element is improved, and the gold layer allows direct die-bonding of a laser chip or the like. Further, since light intercepting structure and interconnection can be provided at the signal processing circuit portion simultaneously with the formation of gold layer for the bonding pad portion, the number of manufacturing steps can be reduced.

Abstract: A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.

Abstract: A circuit assembly comprising a substrate, a first set of contacts, a second set of contacts, and a third set of contacts. Also, a plurality of electrically conductive lines located on the substrate providing electrical connection between the first set of contacts, the second set of contacts, and the third set of contacts, wherein the plurality of electrically conductive lines are configured such that data can be transferred between the first set of contacts, the second set of contacts and the third set of contacts. A first die is electrically connected to the first set of contacts, and a molding compound surrounds the substrate, wherein the molding compound is formed such that the second set of contacts is exposed allowing electrical connection of the second die to the second set of contacts.

Abstract: A process for forming a smooth conformal refractory metal film on an insulating layer having a via formed therein. This process provides extremely good planarity and step coverage when used to form contacts in semiconductor circuits and, in addition, offers improved wafer alignment capability as well as enhanced reliability which result from the smooth surface morphology. The process includes forming contact openings through an insulating layer to a semiconductor substrate; depositing a first blanket layer of titanium using deposition conditions that provide a conformal film that exhibits good step coverage at the contact opening; and forming a second blanket layer of titanium using deposition conditions that provide reduced surface asperity height. The process is ideally suited to forming an electrical interconnection system for semiconductor integrated circuit devices such as static or dynamic random access memories and is particularly useful in VLSI devices that incorporate multiple levels of interconnect.

Abstract: An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of the first transistor, and a quenching element having a terminal connected to a base terminal of the first transistor. The quenching element is formed within the base region or the emitter region of the first transistor.

Abstract: A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region.

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: In a semiconductor integrated circuit device using a MOS type transistor as a transistor for the output of a great current, the source and drain of the transistor is formed by connecting in parallel a plurality of source regions and drain regions surrounded by a gate electrode.

Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

Abstract: A thin-film microstructure sensor includes a substrate having an insulation layer. A thin-film platinum temperature-sensitive resistor is provided on the insulation layer of the substrate, the thin-film platinum temperature-sensitive resistor comprising a platinum layer, the platinum layer having a maximum crystal grain size above a reference grain size of 800 .ANG.. The thin-film platinum temperature-sensitive resistor is formed by a sputtering process to provide a temperature coefficient of resistance TCR above a reference TCR level of 3200 ppm.

Abstract: Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Abstract: The circuit-integrating light-receiving element of this invention includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type formed over the semiconductor substrate; a first semiconductor layer of the first conductivity type for dividing the first semiconductor layer into semiconductor regions of the second conductivity type; light-detecting sections being constituted by the divided semiconductor regions and underlying regions of the semiconductor substrate, a divided photodiode being composed of the light-detecting sections; a second semiconductor layer of the second conductivity type formed only in the vicinity of the first semiconductor layer of the first conductivity type functioning as a division section of the divided photodiode and within the regions of the semiconductor substrate forming the respective light-detecting sections; and a second semiconductor layer of the first conductivity type formed in a surface region of the first semicon

Abstract: A thermally-enhanced flip chip integrated circuit (IC) package has a package substrate to which an IC die is bonded. A thermally-conductive heatspreader, having planar dimensions larger than the IC die, is thermally bonded at or near its center to an upper surface of the IC die. A plurality of cooling extensions are formed that protrude from a lower surface (the surface closest to the package substrate) of the heatspreader so as to create passageways through which cooling air may flow. In one embodiment, the cooling extensions are parallel fins that protrude transversely from the lower surface of the heatspreader, thereby forming U-shaped channels. In another embodiment, the cooling extensions are an array of fin pins that protrude transversely from the lower surface of the heatspreader.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate, a stiffener, a heat spreader, and an optional heat sink. The chip includes multiple I/O pads arranged upon an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The stiffener, a rigid member able to retain its shape during C4 heating, may be attached to the upper surface of the substrate prior to the C4 process, helping the substrate maintain its planarity during and after the C4 process. The stiffener has an opening dimensioned to receive the chip and exposing the first set of bonding pads. Following the C4 process, a first space between the underside surface of the chip and the upper surface of the substrate is filled with an underfill material.

Abstract: The present invention provides a semiconductor package comprising: an electrically conductive base plate having a first surface comprising first, second and third regions; a semiconductor chip provided on the first region of the electrically conductive base plate and the semiconductor chip having at least a first electrode and at least a second electrode; an insulation layer provided on the third region of the electrically conductive base plate; and an electrically conductive thin film pattern laminated on the insulation layer and the electrically conductive thin film pattern being electrically connected to the first electrode of the semiconductor chip, so that the electrically conductive thin film pattern and the first electrode have a first variable potential, wherein the second electrode is connected directly to the second region of the electrically conductive base plate so that the second electrode and the electrically conductive base plate has a second fixed potential which is different from the first va

Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

Abstract: A method of manufacturing a ferroelectric transistor is provided by which the characteristic of the transistor is not degraded because of a heated process. The ferroelectric transistor has a gate unit on the underlying structure. The gate unit includes a gate electrode, a ferroelectric film and a gate insulation film deposited on one another in this order. A channel layer is provided on the gate insulation film. A first main electrode and a second main electrode are provided in a spaced apart manner on the channel layer. The channel layer is used as a channel in operating the transistor. Thus, the carrier density of the channel is controlled by using the spontaneous polarization of the ferroelectric film.