Abstract: The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

Abstract: The present invention is directed to a novel semiconductor device and a method for making same. As disclosed herein, a gate dielectric comprised of epitaxial metal oxide is positioned above a semiconducting substrate. A gate conductor comprised of an epitaxial conductive material is positioned above the gate dielectric. The method comprises forming a layer of an epitaxial metal oxide above a semiconducting substrate, forming a layer of epitaxial conductive material above the layer of epitaxial metal oxide, and forming a source/drain region.

Abstract: An Insulated Gate Bipolar Transistor includes a semiconductor substrate of a first conductivity type forming a first electrode of the device, a semiconductor layer of a second conductivity type superimposed over said substrate, a plurality of body regions of the first conductivity type formed in the semiconductor layer, a first doped region of the second conductivity type formed inside each body region, an insulated gate layer superimposed over portions of the semiconductor layer between the body regions and forming a control electrode of the device, a conductive layer insulatively disposed over the insulated gate layer and contacting each body region and each doped region formed therein, the conductive layer forming a second electrode of the device.

Abstract: A semiconductor device packaged in a plastic package provided with a semiconductor device chip, a plurality of leads each of which is bonded with each of the bonding pads of the semiconductor device chip, and a plastic mold packaging the semiconductor device chip bonded with the leads, allowing the leads to project themselves from the bottom surface thereof and to extend outward along the bottom surface thereof, wherein each of the leads has a horizontal shape in which the surface of the edge thereof is a half circle, a half ellipse or a half polygon convex toward the inward direction.

Abstract: In the present invention, a precharge circuit includes a precharge supply for setting equal potentials at pairs of spaced signal lines extending in parallel with respect to each other, a pair of switching elements for connecting and disconnecting respective signal lines to the supply, and a short circuit switching element for connecting and disconnecting short circuiting of the signal lines. The short circuit switching element consists of a transistor comprising a source and drain constituted by a pair of impurity regions formed underneath the pair of signal lines so as to correspond to the pair of signal lines and a gate. The gate of the transistor is formed in such a manner that gate length coincides with the widthwise direction of the pair of signal lines.

Abstract: The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area.

Abstract: A solid-state imaging device comprises a plurality of pixels, each pixel comprising a semiconductor substrate; a photo-receiving portion formed in the semiconductor substrate; a detecting region formed in the semiconductor substrate; an insulating film formed on the semiconductor substrate, a gate electrode formed on the insulating film above the region between the photo-receiving portion and the detecting region; and a read-out circuit, which is electrically connected to the detecting portion. A reflection reducing film is formed on the insulating film above the region including at least one part of the photo-receiving portion and excluding at least one part of the detecting portion in the semiconductor substrate. With this solid-state imaging device and with the method for manufacturing the same, a highly sensitive MOS solid-state imaging device and the method for manufacturing the same are provided.

Abstract: Internal electrodes and external lead wiring lines are formed on the front surface of a substrate of a semiconductor device, and solder bumps electrically connected to the external lead wiring lines via through holes are provided on the rear surface of the substrate. A first semiconductor chip is mounted on the surface of the substrate, and a second semiconductor chip is mounted on the rear surface of the substrate. Electrodes of the first semiconductor chip are connected to bonding pads at one side ends of the internal wiring lines, and electrodes of the second semiconductor chip are connected to the bonding pads at the other ends of the internal wiring lines and the external lead wiring lines with bonding wires passing through openings provided in the substrate.

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gage is used as a mask during first and second ion implants.

Abstract: A semiconductor device having at least a first and second type of devices formed in the substrate of the semiconductor device and having a hydrogen free barrier layer formed by implanting nitrogen into a layer of amorphous silicon or polysilicon formed on the surface of the semiconductor device. A hydrogen getter layer is formed on the semiconductor device under the barrier layer. The hydrogen getter layer is removed from portions of the semiconductor device on which salicide layers are to be formed.

Abstract: An active layer is sandwiched between the n-type cladding layer and the p-type cladding layer, forming a light emitting layer forming portion. The n-type cladding layer has a carrier concentration of non-doped or less than 5.times.10.sup.17 cm.sup.-3 on a side thereof close to the active layer, and a carrier concentration of 7.times.10.sup.17 -7.times.10.sup.18 cm .sup.-3 on a side thereof remote from the active layer. With this structure, it is possible to suppress to a minimum the deterioration of crystallinity at an interface between the active layer and the n-type cladding layer as well as in the active layer. thereby providing a semiconductor light emitting device high in brightness.

Abstract: A stacked structure of a semiconductor package mainly comprises a first chip, a second chip, a substrate and a lead frame. The first chip and the second chip are attached on the surface of the substrate by a plurality of solder bumps by means of flipchip bonding. Then, the first chip, the second chip and the substrate form a stacked structure. A plurality of plugs of the substrate is provided along an edge of the substrate so as to attach to a plurality of receptacles of the lead frame to form a semiconductor device. The plugs are attached to the receptacles of the lead frame by silver paste to form a semiconductor device in such a way that the first chip and the second chip electrically connect to the lead frame. In addition, the lead frame is bent to form a plurality of fingers, which is placed in a space that is formed by a sidewall of the chip and a surface of the substrate while it is assembled.

Abstract: A heatsink mounted to an electronic device having an area substantially greater than that of the device includes a heatpipe in the heatsink for transferring heat within the heatsink to reduce thermal gradients therein.

Abstract: An infrared solid-state image sensor comprises a semiconductor substrate, a first diaphragm, supported on the semiconductor substrate via a first support portion, for supporting a hot junction of thermocouples for converting a temperature change, caused by irradiation of infrared rays to an infrared absorption layer, to an electric signal, and the infrared absorption layer, and a second diaphragm, supported on the semiconductor substrate via a second support portion, for supporting a wiring portion for outputting a signal from the hot junction of the thermocouples.

Abstract: In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.

Abstract: A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.

Abstract: A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide which is composed of the same constituent elements as those of the compound oxide superconductor material of the superconductor layers but with an atomic ratio which does not present a superconductivity characteristics. In addition, the superconductor layers and the insulator layer are continuously formed while supplying oxygen.

Abstract: A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.

Abstract: A method for manufacturing a semiconductor structure having a via hole is provided. The method includes steps of providing a base, forming a pad on the base, forming a device on the pad, forming a dielectric layer over the device and the base, executing a planarization process with etch back, and etching the dielectric layer to form the via hole. The manufactured semiconductor structure has a dielectric layer having therein the via hole, a device under the dielectrc layer, and a pad under the device for raising the device. The method and structure can prevent a residue due to planarization process from being remained between the dielectric layer and the device.