Abstract: A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.

Abstract: A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.

Abstract: On a surface of a semiconductor chip having a longer side and a shorter side, a line of a plurality of first pads and a line of a plurality of second pads are arranged in the shape of a cross. Upon multibit expansion, increase in length of the longer side of semiconductor chip can be suppressed even though the number of pads is increased by additionally providing the second pad. In addition, there is no need to reduce the pitch between pads. Thus, a semiconductor memory device allowing multibit expansion is provided without an increase in size of the chip and the pad or reduction in pitches between pads and between pins.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: A packaging structure is capable of electrically connecting an external lead to a pad of a semiconductor chip by directly bonding the external lead to the pad of the semiconductor chip without an adhesive, which requires no resin sealing. The packaging structure comprises a lead member 20 having an fitting part with a U-shaped cross section, which can be fit into the semiconductor chip 10 from the end part thereof, and the fitting part pinches the semiconductor chip by means of an elastic restoration force or a plastic deformation, thereby allowing a contact point 20a at one end of the lead member 20 to directly bring into contact with the pad part 11 of the semiconductor chip and, at the same time, the fitting part is provided with a construction for insulating the lead member from the semiconductor chip in the internal circumference except for the contact point.

Abstract: Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

Abstract: In a preferred embodiment, an electronic power device heatsink clamping system, including: a heatsink; at least one electronic power device disposed adjacent a side of the heatsink; at least one clamping spring, having first and second ends, disposed so as to press the at least one electronic device against the side of the heatsink; and a pressure enhancing member pressing against the at least one clamping spring, intermediate the first and second ends, causing the clamping spring to act as a simple beam spring.

Abstract: Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially.

Abstract: A semiconductor device comprising a plurality of bump electrodes wherein signal pins requiring electrical connection are assigned in sequence from the bump electrodes at the outermost periphery near the edge of the semiconductor device to the bump electrodes in an interior area of the semiconductor device, and no-connection pins requiring no electrical connection are assigned to the remaining bump electrodes, is provided. Circuit board cost is thus reduced, and the ease of mounting the semiconductor device to the circuit board is improved.

Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.

Abstract: A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Abstract: A vertically mountable semiconductor device including a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, the semiconductor device may be laminated to one or more adjacent semiconductor devices. The present invention also includes a method of attaching the semiconductor device to a carrier substrate. Preferably, solder paste is applied to terminals on the carrier substrate. The semiconductor device is oriented vertically over the carrier substrate, such that the bumped bond pads align with their corresponding terminals. The bumps are placed into contact with the solder paste. The bumps and solder paste are then fused to form a joint between each of the bond pads and respective terminal, establishing an electrically conductive connection therebetween and imparting structural stability to the semiconductor device.

Abstract: A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal.

Abstract: A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element includes:forming first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method;forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; andannealing at a temperature of 300.degree. C. to 850.degree. C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required of a BPSG film, and it has superior self-flattening characteristics in itself.

Abstract: An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween.

Abstract: A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.

Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

Abstract: An improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. A silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die.

Abstract: A semiconductor device includes a buffer region having buffers and disposed along a side of a semiconductor chip; a pad region having pads corresponding to the buffers and disposed outside the buffer region on the semiconductor chip; signal lines connecting the buffers to corresponding pads; and power supply lines and ground lines connected to extra pads, either of the power supply lines or the ground lines being partially superimposed on part of and separated from the signal lines by insulating layers.

Abstract: A multi-chip memory module comprises multiple standard, surface-mount-type memory chips stacked on top of each other, and a pair of printed circuit boards mounted on opposite sides of the memory chips to electrically interconnect the memory chips. Each printed circuit board has vias that are positioned to form multiple rows, with each row of vias used to connect the printed circuit board to a respective memory chip. The vias falling along the bottom-most row of each printed circuit board are also exposed and are used to surface mount the multi-chip module to pads of a memory board.