Patents Examined by Mamadou Diallo
  • Patent number: 10290535
    Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 14, 2019
    Inventors: Chun-Te Ho, Shih-Yu Chang, Da-Wei Lin, Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 10241371
    Abstract: A thin film transistor, a method for manufacturing the same, an array substrate and a display device are provided. The method for manufacturing a thin film transistor includes: providing a substrate; forming an active layer and a light shielding layer covering the active layer on the substrate by a patterning process, the light shielding layer being formed of a photoresist material; and forming a source-drain electrode layer and a passivation layer covering the source-drain electrode layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 26, 2019
    Inventors: Hefei Li, Xianxue Duan, Chengcheng Wang
  • Patent number: 10235261
    Abstract: A randomness testing apparatus is disclosed. A randomness testing apparatus according to an embodiment includes a randomness testing module to conduct a randomness test on physically unclonable function (PUF)-based hardware and a processing device to determine whether the PUF-based hardware is defective on the basis of a randomness test result.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 19, 2019
    Assignee: ICTK Holdings Co., Ltd.
    Inventors: Dong Kyue Kim, Byong Deok Choi, Kwang Hyun Jee
  • Patent number: 10229826
    Abstract: A method for depositing a metal layer on a barrier layer includes a) arranging a substrate in a processing chamber. The substrate has been exposed to at least one of air and/or oxidizing chemistry and includes a barrier layer and one or more underlying layers, wherein the barrier layer includes a material selected from a group consisting of tantalum nitride, titanium nitride, tantalum and titanium. The method includes b) supplying a gas selected from a group consisting of hydrazine, a gas including fluorine species, a gas including chlorine species, derivatives of hydrazine, ammonia, carbon monoxide, a gas including amidinates, and/or a gas including metal organic ligands to the processing chamber for a predetermined period to remove oxidation from the barrier layer. The method includes c) depositing a metal layer on the barrier layer after b). The metal layer includes a metal selected from a group consisting of cobalt, copper, tungsten, ruthenium, rhodium, molybdenum, and nickel.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: March 12, 2019
    Inventors: Raihan Tarafdar, Shruti Thombare, Jeong-Seok Na, Raashina Humayun, Chiukin Steven Lai
  • Patent number: 10224289
    Abstract: A display device according to an exemplary embodiment includes a substrate including a display area and a non-display area. An alignment mark is positioned in the non-display area. A protective layer is positioned around the alignment mark in the non-display area and separated from the alignment mark in a direction parallel to an upper surface of the substrate. A supporting member is positioned between the alignment mark and the protective layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 5, 2019
    Inventors: Hun Kim, Sung Won Doh, Ki Seong Seo, Hwa Dong Jung
  • Patent number: 10224421
    Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Xinyu Bao, Chun Yan, Hua Chung, Schubert S. Chu, Satheesh Kuppurao
  • Patent number: 10217630
    Abstract: A method of forming a silicon-containing film includes: an adsorption step of supplying a silicon-containing gas represented by a general formula XSiCl3 (wherein X is an element whose bonding energy with Si is smaller than bonding energy of a Si—Cl bond) into a processing chamber accommodating substrates to cause the silicon-containing gas to be adsorbed to a surface of each of the substrates; and a reaction step of supplying a reaction gas reacting with the silicon-containing gas into the processing chamber to cause the silicon-containing gas adsorbed to the surface of each of the substrates to react with the reaction gas.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 26, 2019
    Inventors: Tsubasa Watanabe, Yamato Tonegawa
  • Patent number: 10217893
    Abstract: A method of passivating semiconductor devices using existing tools of junction isolation and phosphosilicate glass (PSG)/borosilicate glass (BSG) etch via room temperature wet chemical growth (RTWCG) processes is provided. Back side processing of the semiconductor device achieves passivation and junction isolation in a single step, while front side processing achieves passivation, PSG/BSG etch, anti-reflection coating and potential induced degradation (PID) mitigation simultaneously. A modified solar cell fabrication method is then provided by integrating the passivation formation method into conventional solar cell manufacturing systems. The resulting solar cells comprise a semiconductor substrate having a front surface and a back surface. The front surface is coated with a SiOx layer less than 50 nm thick, over which a SiNx layer is deposited. On the back surface, another SiOx layer is coated. Experimental data shows high efficiency and mitigated PID of the solar cells.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: February 26, 2019
    Inventors: Gregory C. Knight, Horia M. Faur, Maria Faur
  • Patent number: 10199387
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Patent number: 10199238
    Abstract: A cooling apparatus includes a discrete module and a plastic housing. The discrete module includes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of the discrete module. The plastic housing includes a first singular plastic part which receives the discrete module and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has a cutout which exposes at least part of the first cooling plate and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of the discrete module at a side of the discrete module with the first cooling plate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Inpil Yoo, Andreas Grassmann
  • Patent number: 10199580
    Abstract: An organic EL device includes an anode, an emitting layer, an electron transporting zone and a cathode in this sequence, in which the electron transporting zone contains an aromatic heterocyclic derivative represented by a formula (1) below. In the formula (1), X1 to X3 are a nitrogen atom or CR1, and A is represented by a formula (2) below. In the formula (2), L1 is s single bond or a linking group, and HAr is represented by a formula (3) below.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 5, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Sayaka Mizutani, Takayasu Sado
  • Patent number: 10192917
    Abstract: A photosensor is formed within a semiconductor substrate layer having a front side and a back side. An isolation structure delimits an active region of the semiconductor substrate layer which includes a charge collecting region. The front side of semiconductor substrate layer includes a charge transfer circuit. A reflecting mirror is mounted at the back side of the semiconductor substrate layer. The reflecting mirror includes a pupil opening configured to admit light into the active region at the back side. An underside reflective surface of the reflecting mirror is configured to reflect light received from the active region back into the active region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Bastien Mamdy
  • Patent number: 10192890
    Abstract: A transistor display panel including: a substrate; a gate electrode disposed on the substrate; a semiconductor that overlaps the gate electrode; an upper electrode disposed on the semiconductor; a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor; a source electrode connected with the source connection member and the upper electrode; and a drain electrode connected with the drain connection member.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Display Co., Ltd
    Inventor: Jae-Hyun Park
  • Patent number: 10186561
    Abstract: The present disclosure provides an array substrate and a manufacturing method thereof and an organic light-emitting display apparatus. The array substrate comprises a plurality of sub-pixel zones, each of which comprising a light-emitting unit provided above a base substrate, wherein the light-emitting unit is formed to comprise a concave or convex structure, so that the light-emitting area of the light-emitting unit is greater than the projected area of the light-emitting unit onto the base substrate. Compared to the prior art, the present disclosure can increase the amount of light emission in each sub-pixel zone, so that the view angle of the display may be increased and the display effect may be improved.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 22, 2019
    Inventor: Peng Zhang
  • Patent number: 10180514
    Abstract: A disclosed method includes measuring properties of a formation with a logging tool disposed in a borehole. The method also includes acquiring measurement data corresponding to the measured properties of the formation. The method also includes adjusting a control parameter for logging operations of the logging tool based on at least some of the measurement data and an adaptive learning engine within the logging tool.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 15, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Burkay Donderici, Paul F. Rodney
  • Patent number: 10175387
    Abstract: In an approach, a computer receives an observation dataset that identifies one or more ground truth values of an environmental variable at one or more times and a reforecast dataset that identifies one or more predicted values of the environmental variable produced by a forecast model that correspond to the one or more times. The computer then trains a climatology on the observation dataset to generate an observed climatology and trains the climatology on the reforecast dataset to generate a forecast climatology. The computer identifies observed anomalies by subtracting the observed climatology from the observation dataset and forecast anomalies by subtracting the forecast climatology from the reforecast dataset. The computer then models the observed anomalies as a function of the forecast anomalies, resulting in a calibration function, which the computer can then use to calibrate new forecasts received from the forecast model.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 8, 2019
    Assignee: The Climate Corporation
    Inventors: Alex Kleeman, Holly Dail
  • Patent number: 10177192
    Abstract: An image sensor is provides. The image sensor may include first and second photodiodes, a first color filter shared by the first and the second photodiodes, and first and second floating diffusion regions coupled to the first and the second photodiodes, respectively.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 8, 2019
    Assignee: SK Hynix Inc.
    Inventor: Won-Jun Lee
  • Patent number: 10177195
    Abstract: A micro-light emitting diode (LED) display panel and a method of forming the display panel, the micro-LED display panel having a monolithically grown micro-structure including a first color micro-LED that is a first color nanowire LED, and a second color micro-LED that is a second color nanowire LED.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Kunjal Parikh, Peter L. Chang
  • Patent number: 10170342
    Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Shu-Kwan Lau
  • Patent number: 10164120
    Abstract: A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Katsuaki Tochibayashi, Satoru Okamoto, Akihisa Shimomura