Patents Examined by Mamadou Diallo
  • Patent number: 9958494
    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung
  • Patent number: 9960380
    Abstract: An organic light emitting diode and an organic light emitting display device, the organic light emitting diode including a first electrode and a second electrode facing each other; an emission layer between the first electrode and the second electrode; and a hole transport layer between the first electrode and the emission layer, wherein the hole transport layer includes an organic material and a dipole material, the dipole material including a first component and a second component, the first component having a polarity different from that of the second component and the first component and the second component being combined with each other.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Chan Kim, Won Jong Kim, Eung Do Kim, Dong Kyu Seo, Da Hea Im, Sang Hoon Yim, Chang Woong Chu
  • Patent number: 9960261
    Abstract: A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9947539
    Abstract: Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state while the materials in the selected zones remain hydrophilic.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 17, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ludovic Godet, Srinivas D. Nemani, Tobin Kaufman-Osborn
  • Patent number: 9947588
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Patent number: 9941282
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Patent number: 9934990
    Abstract: A cooling apparatus is manufactured by: receiving a discrete module by a first singular part, the discrete module including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound, and a first cooling plate at least partly uncovered by the mold compound; attaching a second singular part to a periphery of the first part to form a housing, the housing surrounding a periphery of the discrete module, the second part having a cutout which exposes the first cooling plate and a sealing structure facing a side of the discrete module with the first cooling plate; and filling the sealing structure with a sealing material which forms a water-tight seal around the periphery of the discrete module at the side of the discrete module with the first cooling plate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies AG
    Inventors: Inpil Yoo, Andreas Grassmann
  • Patent number: 9929031
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: John C. Johnson, Eric J. Moret, Lawrence M. Palanuk, Gregory A. Stone
  • Patent number: 9922980
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming a diamond film on the substrate, etching the diamond film to form a first trench that extends to the substrate, epitaxially growing a first semiconductor material in the first trench to form a first semiconductor fin structure, and removing an upper portion of the diamond film to expose an upper portion of the first semiconductor fin structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 20, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 9917271
    Abstract: A light-emitting device in which different electrodes in a work function are used in a first light-emitting element and a second light-emitting element are provided. A light-emitting device includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first electrode, an EL layer, and a second electrode in this order. The second light-emitting element includes a third electrode, the EL layer, and the second electrode in this order. The EL layer includes a first light-emitting layer, a layer, and a second light-emitting layer in this order. The structure of the first light-emitting layer is different from the structure of the second light-emitting layer. The first light-emitting element and the second light-emitting element are different in a carrier-injection property.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shogo Uesaka, Nobuharu Ohsawa
  • Patent number: 9911701
    Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 6, 2018
    Assignee: NIKON CORPORATION
    Inventor: Tomoharu Fujiwara
  • Patent number: 9911646
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9899297
    Abstract: In a method of manufacturing a semiconductor device, a thermal treatment is performed on a substrate, thereby forming a defect free layer in an upper layer of the substrate, where a remaining layer of the substrate is a bulk layer. A density of defects in the bulk layer is equal to or more than 1×108 cm?3, where the defects are bulk micro defects. An electronic device is formed over the defect free layer. An opening is formed in the defect free layer such that the opening does not reach the bulk layer. The opening is filled with a conductive material, thereby forming a via. The bulk layer is removed so that a bottom part of the via is exposed. A density of defects in the defect free layer is less than 100 cm?3.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pu-Fang Chen, Victor Y. Lu
  • Patent number: 9899264
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Patent number: 9899516
    Abstract: Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO3—SrTiO3 interface. However, the strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Compositionally grading of PbZr1-xTixO3 ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable significantly enhanced performance of ferroelectric non-volatile memories.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 20, 2018
    Assignee: DREXEL UNIVERSITY
    Inventors: Zongquan Gu, Mohammad Anwarul Islam, Jonathan Eli Spanier
  • Patent number: 9889472
    Abstract: Disclosed is a method of manufacturing a device (1) comprising a plurality of micro-machined ultrasonic transducer cells (100) in a first region (10) on a substrate (30) and a plurality of interconnects (200) in a second region (20) on said substrate, each of said cells comprising a first electrode (110) separated by a cavity (130) from a second electrode (120) supported by a membrane (140), the method comprising forming a dielectric layer stack (11, 13, 15, 17) over the substrate, said dielectric layer stack defining the respective membranes of the micro-machined ultrasonic transducers in the first region; reducing the thickness of the dielectric layer stack in the second region by partially etching away the dielectric layer stack in the second region; etching a plurality of trenches (22) in the reduced thickness portion of the dielectric layer stack, each of said trenches exposing a conductive contact (210) in the second region; and filling said trenches with a conductive material.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: February 13, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Ruediger Mauczok, Bout Marcelis
  • Patent number: 9882176
    Abstract: In an organic electroluminescence device (100), a hole transport layer (22) is formed of a cured resin obtained by a ring opening polymerization of a polymerizable compound (a) containing a ring opening polymerizable group in the presence of a polymerization initiator (b). In addition, both of a maximum peak height Rp and a maximum valley depth Rv in an upper surface of the hole transport layer (22) are less than or equal to 14 nm. Accordingly, an organic electroluminescence device having excellent mass productivity and high luminescent efficiency is realized.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 30, 2018
    Assignee: PIONEER CORPORATION
    Inventors: Takahito Oyamada, Naoya Yuzuriha
  • Patent number: 9881945
    Abstract: A method of manufacturing a thin film transistor is disclosed. The method of manufacturing the thin film transistor includes: manufacturing a substrate; forming an oxide semiconductor layer on the substrate; forming a pattern including an active layer through a patterning process; forming a source and drain metal layer on the active layer; and forming a pattern including a source electrode and a drain electrode through a patterning process, an opening being formed between the source electrode and the drain electrode at a position corresponding to a region of the active layer used as a channel, wherein the step of forming the pattern including the source electrode and the drain electrode through a patterning process includes: removing a portion of the source and drain metal layer corresponding to the position of the opening through dry etching. The method may also be used to manufacturing a thin film transistor.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Qiyu Shen
  • Patent number: 9880439
    Abstract: A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 30, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zheng Liu
  • Patent number: 9871003
    Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 16, 2018
    Assignee: NIKON CORPORATION
    Inventor: Tomoharu Fujiwara