Patents Examined by Mardochee Chery
  • Storage control apparatus for managing pages of cache and computer-readable storage medium storing program
    Patent number: 10664393
    Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 26, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima Abe
  • Transmitting contents of an operation field to a media controller
    Patent number: 10664410
    Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 26, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Derek Alan Sherlock, Russ W Herrell
  • Application driven hardware cache management
    Patent number: 10664199
    Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Subramanya R. Dulloor, Rajesh M. Sankaran, David A. Koufaty, Christopher J. Hughes, Jong Soo Park, Sheng Li
  • Device and method for assisting processor in reading data
    Patent number: 10657063
    Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yen-Ju Lu, Chao-Wei Huang
  • Memory component with multiple command/address sampling modes
    Patent number: 10650872
    Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
  • Apparatus and method for handling page invalidate requests in an address translation cache
    Patent number: 10649907
    Abstract: An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 12, 2020
    Assignee: Arm Limited
    Inventor: Abhishek Raja
  • Extending flash storage lifespan and data quality with data retention protection
    Patent number: 10650885
    Abstract: One technique for extending flash storage lifespan and data quality with data retention protection includes: determining whether page data included in a page in a solid state drive (SSD) has been copied to another storage; in the event that the page data has not been copied to the other storage: determining whether the page data is to be refreshed; and in the event that the page data is determined to be refreshed, refreshing at least the page data. Another technique includes determining whether a number of times a page has been read exceeds a read threshold, or an amount of time since the page was written exceeds a retention threshold.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 12, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Supporting multiple page lengths with unique error correction coding via galois field dimension folding
    Patent number: 10649841
    Abstract: Disclosed are methods and devices for supporting multiple page lengths with unique error correction coding via Galois field dimension folding. In one embodiment, a method comprises receiving a write instruction, the write instruction including user data; generating extended user data based on the user data, the extended user data including at least one symbol comprising a bit of the user data and a pre-stored bit pattern; generating parity data by encoding the extended user data; generating parity extension data by encoding the bit of the user data; writing a codeword to a page of a non-volatile memory device, the codeword including the parity extension data, the user data, and the parity data.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 12, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Key invalidation in cache systems
    Patent number: 10642745
    Abstract: Techniques are disclosed relating to invalidating keys in a cache. In some embodiments, a computer system may implement a cache for a data store, where the cache stores a data set and is organized such that a stored data item of the data set is specified by a corresponding key having one or more portions. The computer system may store metadata for the cache, where the metadata includes nodes organized in a hierarchy. The computer system may receive a request to invalidate one or more keys of the cache, and may invalidate a particular node within the metadata based on a key value corresponding to the request.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 5, 2020
    Assignee: salesforce.com, inc.
    Inventor: Nick Hansen
  • System and method for creating high frequency snapshots of an entity in a virtualized environment
    Patent number: 10642518
    Abstract: A system and method for capturing high frequency snapshots of an entity includes creating, by a storage sub-system associated with a distributed storage system of a virtualized environment, a cached configuration of an entity within the storage sub-system, capturing, by the storage sub-system, a snapshot of the entity from the cached configuration based on a schedule of a snapshot policy, including sending, by the storage sub-system, the snapshot to a repository indicated in the snapshot policy, and determining, by the storage sub-system, that a configuration file associated with the entity has been updated. The system and method also includes updating, by the storage sub-system, the cached configuration based upon the configuration file that has been updated.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 5, 2020
    Assignee: NUTANIX, INC.
    Inventors: Angshuman Bezbaruah, Bharath Kumar Beedu, Kiran Tatiparthi, Mayur Sadavarte, Pranab Patnaik, Praveen Padia
  • Reduced peak self-refresh current in a memory device
    Patent number: 10622052
    Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Vijayakrishna J. Vankayala
  • Data storage device with bytewise copy
    Patent number: 10620870
    Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Sanjeev N. Trika
  • Application cache replication to secondary application(s)
    Patent number: 10613978
    Abstract: Replicating a primary application cache that serves a primary application on one network node into a secondary application cache that serves a secondary application on a second network node. Cache portions that are within the primary application cache are identified, and then identifiers (but not the cache portions) are transferred to the second network node. Once these identifiers are received, the cache portions that they identify may then be retrieved into the secondary application caches. This process may be repeatedly performed such that the secondary application cache moves towards the same state as the primary application cache though the state of the primary application cache also changes as the primary application operates by receiving read and write requests.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nikhil Teletia, Jae Young Do, Kwanghyun Park, Jignesh M. Patel
  • Determining membership among storage systems synchronously replicating a dataset
    Patent number: 10613779
    Abstract: Embodiments are directed to determining active membership among a set of storage systems synchronously replicating a dataset. Determining active membership among a set of storage systems synchronously replicating a dataset includes determining that a membership event corresponds to a change in membership to the set of storage systems synchronously replicating the dataset. Determining active membership further includes applying, in dependence upon the membership event, one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset. Determining active membership also includes, for one or more I/O operations directed to the dataset, applying the one or more I/O operations to the dataset synchronously replicated by the new set of storage systems.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 7, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Connor Brooks, Thomas Gill, David Grunwald, Ronald Karr, Aswin Karumbunathan, Naveen Neelakantam, Zoheb Shivani, Kunal Trivedi
  • Time-restricted access to file data
    Patent number: 10606769
    Abstract: A file data access method and a computer system, where the method includes accessing a page global directory (PGD) of the process using PGD space when accessing first file data by a process, determining, based on access to the PGD and according to a first virtual address of the first file data in file system space, a first PGD entry in the PGD, linking a file page table of the process to the first PGD entry, where the file page table points to a physical address of the file data such that a processor retrieves a first physical address of the first file data in a memory according to the first virtual address using the PGD and the file page table, and accessing the first file data according to the first physical address.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 31, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qun Yu, Jun Xu, Yuangang Wang
  • Data writing device and method
    Patent number: 10585622
    Abstract: A data writing device includes secondary storages, an interface circuit which obtains data, and a computer apparatus which writes the data obtained in one of the secondary storages. The computer apparatus includes writing processes corresponding to the secondary storages as an application, respectively; a monitoring process which detects quantities of data whose writing is finished in the secondary storages; and a data distribution process which selects a secondary storage as a target for next writing based on requested data quantities of the secondary storages and the finished data quantities thereof, and instructs a writing process corresponding to the secondary storage as a target for next writing to write.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 10, 2020
    Assignee: TOYO Corporation
    Inventors: Yoshiyuki Saitoh, Chunshan Luo
  • Optimized sequential writes on mirrored disks
    Patent number: 10585612
    Abstract: Embodiments for optimizing sequential write operations in a data deduplication environment by one or more processors. Similar data deduplication signatures for stored data at all storage devices in one or more storage systems may be maintained. A deduplication signature associated with a write operation at a storage device may be compared to the similar data deduplication signatures. Results of the comparison with each of the other storage devices may be shared prior to performing the write operation.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Krishnasuri Narayanam, Sarvesh Patel, Sachin C. Punadikar, Subhojit Roy
  • Effective address based instruction fetch unit for out of order processors
    Patent number: 10579384
    Abstract: Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes receiving, by an instruction fetch unit (IFU), a request to fetch an instruction for execution, wherein the instruction includes an effective address (EA). The IFU can further access an instruction cache directory (I-directory) using the EA of the requested instruction to determine whether the EA of the requested instruction matches an EA stored in an associated instruction cache (I-cache). An instruction cache (I-cache) can output the requested instruction in response to or based at least in part on determining that the requested instruction EA matches an entry in the I-cache. A decode unit can decode the requested instruction output by the I-cache.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert A. Philhower, Balaram Sinharoy
  • Memory network with memory nodes controlling memory accesses in the memory network
    Patent number: 10572150
    Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: February 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sheng Li, Norman Paul Jouppi, Paolo Faraboschi, Michael R. Krause
  • Efficient management of point in time copies of data in object storage by sending the point in time copies, and a directive for manipulating the point in time copies, to the object storage
    Patent number: 10572347
    Abstract: A computer program product is provided for managing point in time copies of data in object storage. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to create point in time copies of data, and send the point in time copies of the data to an object storage system. Also, the program instructions are executable by the processor to cause the processor to send a directive for manipulating the point in time copies of the data.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Basham, Joseph W. Dain, Matthew J. Fairhurst