Abstract: Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one embodiment of the processor comprises: a decoder to decode a plurality of instructions including instructions related to a trusted domain; execution circuitry to execute a first one or more of the instructions to establish a first trusted domain using a first trusted domain key, the trusted domain key to be used to encrypt memory pages within the first trusted domain; and the execution circuitry to execute a second one or more of the instructions to associate a first process address space identifier (PASID) with the first trusted domain, the first PASID to uniquely identify a first execution context associated with the first trusted domain.

Abstract: A memory system includes a nonvolatile memory device; In an embodiment, a memory system comprising: a nonvolatile memory device; a working memory configured to store a first layer and a second layer as firmwares, each of which drives the nonvolatile memory device; a control component configured to control the nonvolatile memory device based on the firmwares; a buffer memory configured to store a first table which is managed by the first layer and a second table which is managed by the second layer; and a memory controller configured to store a descriptor for setting information of the nonvolatile memory device, and interface with the nonvolatile memory device based on control of the control component, wherein the second layer stores position information of the descriptor in the second table, and wherein the first layer accesses the memory controller by referring to the second table.

Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.

Abstract: A technique preserves replication to a storage node. The technique involves, from a first storage node, sending a replication query to a second storage node. The technique further involves, in response to the replication query sent to the second storage node, receiving replication session data from the second storage node. The replication session data describes replication which has terminated from a third storage node to the second storage node for a particular storage object. The technique further involves, based on the replication session data, establishing replication from the first storage node to the second storage node for the particular storage object to preserve use of the particular storage object.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A method and an apparatus for triggering RAID reconstruction are disclosed, to achieve high universality and usability in triggering RAID reconstruction. The method includes: obtaining valid data information of a target storage medium after a change in storage mediums in a RAID is detected (S101); and reconstructing the RAID if the valid data information satisfies a preset reconstruction condition (S102).

Abstract: Aspects of the present disclosure describe a cache system that is co-managed by software and hardware that obviates use of a cache coherence protocol. In some embodiments, a cache would have the following two hardware interfaces that are driven by software: (1) invalidate or flush its content to the lower level memory hierarchy; (2) specify memory regions that can be cached. Software would be responsible for specifying what regions can be cacheable, and may flexibly change memory from cacheable and not, depending on the stage of the software program. In some embodiments, invalidation can be done in one cycle. Multiple valid bits can be kept for each tag in the memory. A vector “valid bit vec” comprising a plurality of bits can be used. Only one of two bits may be used as the valid bit to indicate that this region of memory is holding valid information for use by the software.

Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.

Abstract: Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.

Abstract: A method for managing cache memory in a user device is disclosed. The method comprises stagewise excluding adding data to the cache memory as cache memory fill level increases, the stagewise excluding comprising determining, for each successive stage of cache memory fill level, exclusion of the data from being added to the cache memory according to rules of exclusion of adding of data to the cache memory that are increasingly restrictive.

Abstract: A computer-implemented method of information lifecycle management is disclosed. The computer-implemented method includes reading, by a data processing system of a storage environment, business rules and policies for managing data in storage volumes of the storage environment, the policies being based on the predetermined business rules, and analyzing, by the data processing system, available storage and capacity in the storage environment. The computer-implemented method further includes dynamically prioritizing, by the data processing system, the policies based, at least in part, on results of the analyzing, resulting in prioritized policies, cognitively translating, by the data processing system, one or more of the predetermined business rules into action(s) against one or more of the storage volumes based, at least in part, on the prioritized policies, and executing, by the data processing system, the action(s).

Abstract: A memory system and an operating method thereof are provided. The memory system includes a controller buffer memory, a host interface configured to receive non-linear host physical addresses and write data from a host, a host address translation section configured to map the non-linear host physical addresses to linear virtual addresses, and a host control section configured to buffer the write data in the controller buffer memory according to the linear virtual addresses.

Abstract: Various systems and methods are disclosed for optimizing data segments used during inline data deduplication, among other features and functionality. In one embodiment, such functionality includes buffering data received from a node, where an offset value is associated with the data and a segment size is associated with the buffer, until the buffer becomes full or a trigger event occurs. In response to determining that the buffer is full or that a trigger event has occurred, determining whether the offset value is an integer multiple of the segment size. If the offset value is not an integer multiple of the segment size, the functionality generates a modified segment, and then determines whether that modified segment is a duplicate of data stored in a deduplicated data store. If the modified segment is not a duplicate, the modified segment is stored in the deduplicated data store.

Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Abstract: An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element.

Abstract: One technique for extending flash storage lifespan and data quality with data retention protection includes: determining whether page data included in a page in a solid state drive (SSD) has been copied to another storage; in the event that the page data has not been copied to the other storage: determining whether the page data is to be refreshed; and in the event that the page data is determined to be refreshed, refreshing at least the page data. Another technique includes determining whether a number of times a page has been read exceeds a read threshold, or an amount of time since the page was written exceeds a retention threshold.