Abstract: Aspects of dislocated charge storage for power loss protection in non-volatile memory systems are described. A system includes a power supply having an output power stage with bulk capacitance to supply power for a period of time after a power supply failure. The system also includes a network storage interface device and a non-volatile memory media card both coupled to the power supply for power. The power supply is configured to generate a power loss alert in response to the power supply failure. In turn, the network storage interface device is configured to perform a power loss data protection procedure with the non-volatile memory media card based on the power loss alert and during the period of time that the bulk capacitance can supply power after the power supply failure. The additional capacitance typically needed for power loss protection features is located apart from the non-volatile memory media cards.

Abstract: A memory system includes a nonvolatile memory device; and a controller suitable for processing a write request of first data transmitted from a host device. The controller includes a first processing circuit suitable for generating a read command afforded with a priority, based on the write request; and a second processing circuit suitable for processing the read command according to the priority and thereby reading second data including old data of the first data from the nonvolatile memory device.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: Provided are a computer program product, system, and method for distributing tracks to add to cache to processor cache lists based on counts of processor access requests to the cache. There are a plurality of lists, wherein there is one list for each of the plurality of processors. A determination is made as to whether the counts of processor accesses of tracks are unbalanced. A first caching method is used to select one of the lists to indicate a track to add to the cache in response to determining that the counts are unbalanced. A second caching method is used to select one of the lists to indicate the track to add to the cache in response to determining that the counts are balanced. The first and second caching methods provide different techniques for selecting one of the lists.

Abstract: A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.

Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.

Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.

Abstract: Disclosed aspects relate to accelerator sharing among a plurality of processors through a plurality of coherent proxies. The cache lines in a cache associated with the accelerator are allocated to one of the plurality of coherent proxies. In a cache directory for the cache lines used by the accelerator, the status of the cache lines and the identification information of the coherent proxies to which the cache lines are allocated are provided. Each coherent proxy maintains a shadow directory of the cache directory for the cache lines allocated to it. In response to receiving an operation request, a coherent proxy corresponding to the request is determined. The accelerator communicates with the determined coherent proxy for the request.

Abstract: Provided are a computer program product, system, and method for using cache lists for processors to determine tracks in a storage to demote from a cache. Tracks in the storage stored in the cache are indicated in lists. There is one list for each of a plurality of processors. Each of the processors processes the list for that processor to process the tracks in the cache indicated on the list. There is a timestamp for each of the tracks indicated in the lists indicating a time at which the track was added to the cache.

Abstract: Selective purging of entries of structures associated with address translation. A request to purge entries of a structure associated with address translation is obtained. Based on obtaining the request, a determination is made as to whether selective purging of the structure associated with address translation is to be performed. Based on determining that selective purging is to be performed, one or more entries of the structure associated with address translation are purged. The selectively purging includes clearing the one or more entries of the structure associated with address translation for a host of the computing environment and leaving one or more entries of one or more guest operating systems in the structure associated with address translation. The one or more guest operating systems are managed by the host.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The requester uses each generated prefetch address to prefetch information from the external memory. A prefetch memory may store one or more prefetch programs and a prefetch programmer may be included to select from among stored prefetch programs to program the prefetcher based on an executing process. Each prefetch program may be configured according to a prefetch definition.

Abstract: A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched load microinstructions and provides load requests to the memory system. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks the load requests. The prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The prefetch requester submits the at least one prefetch address to prefetch information from the memory system.

Abstract: A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.

Abstract: Efficient deletion of a shared snapshot and other workflows are described herein, including: determining to delete a shared snapshot associated with a first container, wherein the shared snapshot shares with a second container at least a subset of data values that are stored by the shared snapshot, the determination is based at least in part on the shared snapshot sharing data values with not more than a prescribed number of containers other than the second container and an occurrence of a deletion triggering event; and causing zero or more data values that are stored by the shared snapshot and shared with the second container to be associated with the second container prior to deleting the shared snapshot.

Abstract: Managing memory of a computing environment. A determination is made as to whether a block of memory is being used to back an address translation structure used by a guest program. The block of memory is a block of host memory, and the guest program is managed by a virtual machine manager that further manages the host memory. A memory management action is performed based on whether the block of memory is being used to back the address translation structure.

Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.

Abstract: A method for executing a program region by a computer system with transactional memory support is disclosed. The computer system uses hierarchical locks for executing the program region. Determination is conducted whether a first condition related to a transaction abort is satisfied in beginning a transaction for the program region. If the first condition is satisfied, a bottom level lock corresponding to a bottom level resource among available resources is acquired to execute the program region in the transaction. If a second condition is determined to be satisfied, a next level lock corresponding to next level resource is acquired. If the acquired lock is a top level lock corresponding to a top level resource, the program region is executed without using the transaction.

Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes a purging capability that limits the purging of translation look-aside buffers and other such structures based on the marking.

Abstract: Provided are a computer program product, system, and method for using cache lists for processors to determine tracks in a storage to demote from a cache. Tracks in the storage stored in the cache are indicated in lists. There is one list for each of a plurality of processors. Each of the processors processes the list for that processor to process the tracks in the cache indicated on the list. There is a timestamp for each of the tracks indicated in the lists indicating a time at which the track was added to the cache. Tracks indicated in each of the lists having timestamps that fall within a range of timestamps are demoted.