Patents Examined by Mardochee Chery
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Patent number: 10474517Abstract: A method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device determines a respective operational state of each of one or more processes of the embedded-system device. The embedded-system device stores the respective operational state of each of the one or more processes at a memory location in a respective memory area for the each process in a memory of the embedded-system device. The embedded-system device stores the memory locations associated with the one or more processes in a register in the memory. The embedded-system device obtains, from the register, a memory location of at least one process of the one or more processes. The embedded-system device obtains, based on the memory location of the at least one process, the stored operational state of the at least one process from the respective memory area for the at least one process.Type: GrantFiled: July 18, 2016Date of Patent: November 12, 2019Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLCInventors: Satheesh Thomas, J. Vinodhini, Venkatesan Balakrishnan, Baskar Parthiban
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Patent number: 10467136Abstract: An in-memory cluster computing framework node is described. The node includes storage devices having various priorities. The node also includes a resource monitor to monitor the operation of the storage devices. The node also includes a resource scheduler. When the resource monitor indicates that a storage device is at or approaching saturation, the resource scheduler can migrate data from that storage device to another storage device of lower priority.Type: GrantFiled: October 13, 2018Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Inseok Stephen Choi, Yang Seok Ki
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Patent number: 10467177Abstract: Systems and methods for an Enhanced High Bandwidth Memory (EHBM) are described, utilizing fewer physical wires than a HBM interface with each wire operating at a much higher signaling rate. The same logical signals and commands of HBM are supported over this higher-speed transport, with the resulting lower wire count and reduced signal density allowing use of lower-cost interconnection such as an organic rather than a silicon interposer between GPU and DRAM stack.Type: GrantFiled: December 8, 2017Date of Patent: November 5, 2019Assignee: KANDOU LABS, S.A.Inventors: Amin Shokrollahi, Brian Holden, David Stauffer
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Patent number: 10452562Abstract: Embodiments of the application provide a file access method. A computing node receives a file open request that carries a file identifier. The computing node obtains an index node of a file that is identified by the file identifier. The computing node further obtains, based on the index node, a physical address space of a memory area in a file storage area, in which the file is stored. The computing node allocates a virtual address space to the file, and recodes a virtual-physical address mapping relationship by using a memory page table. The virtual-physical address mapping relationship includes a mapping relationship between the virtual address space and the physical address space.Type: GrantFiled: September 7, 2016Date of Patent: October 22, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Hsing Mean Sha, Qingfeng Zhuge, Guanyu Zhu
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Patent number: 10445230Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes.Type: GrantFiled: December 8, 2017Date of Patent: October 15, 2019Assignee: Macronix International Co., Ltd.Inventor: Ting-Yu Liu
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Patent number: 10437492Abstract: A host device can offload certain copy operations to an I/O adapter device coupled to the host device. The I/O adapter device can perform a copy operation to copy data from a source storage volume to a destination storage volume. The source storage volume and the destination storage volume can be local or remote to the I/O adapter device. The copy operations can be performed for replica creation, online migration or for copy-on-write snapshots.Type: GrantFiled: June 14, 2018Date of Patent: October 8, 2019Assignee: Amazon Technologies, Inc.Inventor: Robert Michael Johnson
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Patent number: 10430082Abstract: A server management method and a server, where the server is divided into two parts, a computing component and a storage component, according to a part maintenance cycle. The computing component and the storage component are connected in a detachable manner. The computing component includes a part with a short maintenance cycle, and the storage component includes a part with a long maintenance cycle. Therefore, the computing component or the storage component can be flexibly replaced during server maintenance, and maintenance efficiency is high.Type: GrantFiled: January 23, 2018Date of Patent: October 1, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jinshui Liu, Tongling Song, Wei Liu
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Patent number: 10430346Abstract: A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.Type: GrantFiled: February 5, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: David Stanely Maxey, Nidish Ramachandra Kamath, Vikas Kumar Agrawal
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Patent number: 10416906Abstract: A method includes determining, by a managing unit of a dispersed storage network (DSN), an addition of a new storage unit to a group of storage units. The DSN includes a logical address space divided into a set of logical address sub-spaces, one of which is allocated to the group of storage units. The method further includes reorganizing, by the managing unit, distribution of the logical address sub-space among the new storage unit and each storage unit in the group of storage units to produce a reorganized logical address sub-space. The allocation includes the new storage unit's portion being between portions of first and second storage units. The method further includes transferring, by the first storage unit, a first group of encoded data slices to the new storage unit and transferring, by the second storage unit, a second group of encoded data slices to the new storage unit.Type: GrantFiled: March 23, 2017Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew D. Baptist, Ravi V. Khadiwala, Manish Motwani, Jason K. Resch
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Patent number: 10409502Abstract: An example method and an example apparatus for writing data into a cache are described herein. The example method includes receiving an IO request write command, where the IO request write command includes metadata of to-be-written data. A first buddy group is obtained from a global buddy queue, and a determination as to whether all metadata of the to-be-written data can be written into the first buddy group is made. If the determination is yes, all the metadata of the to-be-written data is written into the first buddy group, and all the metadata of the to-be-written data is written into a metadata block corresponding to a metadata group to which the first buddy group belongs.Type: GrantFiled: January 10, 2018Date of Patent: September 10, 2019Assignee: Huawei Technologies Co., Ltd.Inventor: Futang Huang
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Patent number: 10409501Abstract: The system and methods disclosed herein relate to an improvement in automated data tiering technology. In these embodiments, users are able to weigh the importance of read, write, and pre-fetch operations in terms of tier placement within the data storage system. Data relocation evaluations are performed by an off-load engine, e.g., a graphics processing unit, which utilizes parallel processing on data arrays/vectors/extents. The data relocation candidates are identified via calculating a mobility score on an extent-by-extent basis. Data are then relocated within the various tiers of the data storage system.Type: GrantFiled: December 7, 2017Date of Patent: September 10, 2019Assignee: EMC IP Holding Company LLCInventors: Peter Kushner, Jonathan Krasner, Chakib Ouarraoui
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Patent number: 10402345Abstract: An apparatus comprises a processor to perform tile-based rendering to build a command buffer without knowledge whether the contents of a cache will be discarded, and a memory to store the command buffer. The processor is to determine a discard state of the cache prior to executing the command buffer, execute the command buffer, and discard or keep the contents of the cache according to the discard state. The command buffer can sample discard control from memory immediately before the processor executes the command buffer. The discard control in memory can be updated after the command buffer is queued and before the processor executes the command buffer.Type: GrantFiled: October 28, 2016Date of Patent: September 3, 2019Assignee: Intel CorporationInventor: Michael Apodaca
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Patent number: 10394458Abstract: Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.Type: GrantFiled: June 7, 2018Date of Patent: August 27, 2019Assignee: Commvault Systems, Inc.Inventors: Amit Mitkar, Andrei Erofeev
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Patent number: 10394585Abstract: A computing device includes a host, one or more guest partitions, and one or more physical devices. A physical device can be virtualized, at least in part, by the host and made available to the guest partitions. A physical device includes both a control plane and a data plane. The host provides direct access to at least part of the data plane of a physical device to a guest partition. However, the host virtualizes the control plane of the physical device, exposing a control plane for the physical device to the guest partition that is not the actual control plane of the physical device. Requests to access (e.g., read, write, modify, etc.) the control plane of the physical device are received by the host from the guest partition, and converted as appropriate to the control plane for the physical device.Type: GrantFiled: March 7, 2017Date of Patent: August 27, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Hadden Mark Hoppert, Christopher L. Huybregts
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Data pattern detecting device, semiconductor device including the same, and operating method thereof
Patent number: 10387579Abstract: A pattern detecting device includes a length comparison unit suitable for comparing lengths of compressed input data and compressed reference data; and a data comparison unit suitable for comparing the compressed input data and the compressed reference data.Type: GrantFiled: November 20, 2014Date of Patent: August 20, 2019Assignees: SK hynix Inc., Industry-University Cooperation Foundation Hanyang UniversityInventors: Dong-Wook Kim, Soo-Yong Kang -
Patent number: 10387243Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.Type: GrantFiled: December 8, 2017Date of Patent: August 20, 2019Assignee: Macronix International Co., Ltd.Inventors: Ting-Yu Liu, Yi-Chun Liu
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Patent number: 10379761Abstract: According to certain aspects, a system can include a client computing device configured to: in response to user interaction, store an identifier associated with a first tag in association with a first file; and in response to instructions to perform a secondary copy operation, forward the first file, a second file, and the identifier associated with the first tag. The system may also include a secondary storage controller computer(s) configured to: based on a review of the identifier associated with the first tag, identify the first file as having been tagged with the first tag; electronically obtain rules associated with the first tag; perform on the first file at least a first secondary storage operation specified by the rules associated with the first tag; and perform on the second file at least a second secondary storage operation, wherein the first and second secondary storage operations are different.Type: GrantFiled: February 26, 2018Date of Patent: August 13, 2019Assignee: Commvault Systems, Inc.Inventors: Manas Bhikchand Mutha, Pavan Kumar Reddy Bedadala, Vinit Dilip Dhatrak, Christopher A. Alonzo
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Patent number: 10379905Abstract: Provided are a computer program product, system, and method for distributing tracks to add to cache to processor cache lists based on counts of processor access requests to the cache. There are a plurality of lists, wherein there is one list for each of the plurality of processors. A determination is made as to whether the counts of processor accesses of tracks are unbalanced. A first caching method is used to select one of the lists to indicate a track to add to the cache in response to determining that the counts are unbalanced. A second caching method is used to select one of the lists to indicate the track to add to the cache in response to determining that the counts are balanced. The first and second caching methods provide different techniques for selecting one of the lists.Type: GrantFiled: March 12, 2018Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
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Patent number: 10372606Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.Type: GrantFiled: September 30, 2016Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Malladi, Jongmin Gim, Hongzhong Zheng
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Patent number: 10360952Abstract: Multiport memory architecture is disclosed herein. An example memory includes an input port, a memory array, and an output port. The input port is coupled to receive data blocks and includes first and second buffers coupled to temporarily store alternate data blocks, and the output port is coupled to provide data blocks from the memory array. The memory array is partitioned into first and second partitions, with the first partition coupled to receive data blocks from the first buffer and the second partition coupled to receive data blocks from the second buffer, and the input port and the memory array are coupled to receive control signals to simultaneously receive a first data block at the first buffer, transfer a second data block from the second buffer to a first address in the second partition, and provide a third data block stored at a third address of the first partition.Type: GrantFiled: December 20, 2016Date of Patent: July 23, 2019Assignee: OmniVision Technologies, Inc.Inventors: Taehyung Jung, Jongsik Na, Sunny Ng