Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.

Abstract: A computer program product is provided for managing point in time copies of data in object storage. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to create point in time copies of data, and send the point in time copies of the data to an object storage system. Also, the program instructions are executable by the processor to cause the processor to send a directive for manipulating the point in time copies of the data.

Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

Abstract: According to some embodiments, a backup storage system receives a request from a client for writing a data segment associated with a file object stored to a storage system. In response to the request, the system writes the data segment to one of many storage units of the storage system. The system determines whether the data segment is associated with a file region of the file object that is frequently accessed. The system writes the data segment in a first of many of write-evict units (WEUs) stored in a solid state device (SSD) operating as a cache memory device for caching data, after it is determined that the data segment is associated with the frequently accessed file region.

Abstract: Dynamic block optimization for space and performance is disclosed, including: determining that a data pattern associated with a data block included in a write request matches a promoted data pattern; and performing the write request by associating the data block with a previously stored copy of the data block without updating an associated reference count. Dynamic block optimization for space and performance further includes determining that a data pattern associated with a data block included in a write request matches a predetermined data pattern; and performing the write request by storing a static representation associated with the data block and not storing the data block, wherein the static representation is usable to generate the data block.

Abstract: Data stored in a hard disk drive (HDD) is processed to generate cache data to be stored in a random access memory (RAM). If a data access request is received from an application and valid cache data corresponding to the access request is present in the RAM, response data is acquired from the RAM, without accessing the HDD, and the response data is transmitted to the source of the access request. If the valid cache data corresponding to the access request is not present in the RAM, response data is acquired from the HDD and the response data is transmitted to the source of the access request. Consequently, the number of times of access to the HDD is reduced.

Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.

Abstract: A hypervisor deduplcation system includes a memory, a processor in communication with the memory, and a hypervisor executing on the processor. The hypervisor is configured to scan a first page, detect that the first page is an unchanged page, check a first free page hint, and insert the unchanged page into a tree. Responsive to inserting the unchanged page into the tree, the hypervisor compares the unchanged page to other pages in the tree and determine a status of the unchanged page as matching one of the other pages or mismatching the other pages in the tree. Responsive to determining the status of the page as matching another page, the hypervisor deduplicates the unchanged page. Additionally, the hypervisor is configured to scan a second page of the memory, check a second free page hint, deduplicate the second page if the free page hint indicates the page is unused.

Abstract: A method of operating a storage device includes receiving a first logical address from a host, determining whether first metadata stored in a volatile memory of the storage device and associated with the first logical address is corrupted, processing the first metadata as an uncorrectable error when the first metadata is determined to be corrupted, providing an error message to the host indicating that an operation cannot be performed on data associated with the first logical address when the first metadata is processed as the uncorrectable error, after the providing of the error message, receiving a second logical address from the host, determining whether second metadata stored in the volatile memory and associated with the second logical address is corrupted, and performing an operation of accessing the non-volatile memory based on the second metadata, when the second metadata is not determined to be corrupted.

Abstract: Replicating a primary application cache that serves a primary application on one network node into a secondary application cache that serves a secondary application on a second network node. Cache portions that are within the primary application cache are identified, and then identifiers (but not the cache portions) are transferred to the second network node. Once these identifiers are received, the cache portions that they identify may then be retrieved into the secondary application caches. This process may be repeatedly performed such that the secondary application cache moves towards the same state as the primary application cache though the state of the primary application cache also changes as the primary application operates by receiving read and write requests.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A memory system including a nonvolatile memory device storing operation logs and map data; a volatile memory for temporarily storing the map data; and a controller flushing the map data from the volatile memory into the nonvolatile memory device by units of map data groups, and rebuilding the map data by selectively reading the map data by the units of map data groups from the nonvolatile memory device into the volatile memory according to the operation logs, wherein the operation logs indicate: locations of first and last pages to store the flushed map data; a start of an error management operation to a program error during the flushing of the map data; and a location of a last page storing normally flushed map data before an occurrence of the program error.

Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.

Abstract: A memory management method is provided. The method includes performing a read retry operation to a target block stripe, and identifying a read retry recording table of the target block stripe; selecting a target read retry index value from one or more first read retry index values according to the one or more first read retry index values in the read retry recording table; using a target read retry option corresponding to the read retry index value to perform a read operation to the target block stripe; in response to determining that the read operation is successful, determining that the read retry operation is completed, and updating the read retry recording table according to the target read retry index value; and determining whether to perform a wear leveling operation to the target block stripe according to the latest read retry recording table.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: A memory controller is used to verify authenticity of data stored in a first memory unit, and includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value, authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating if the data written to the first memory unit is not authentic.

Abstract: A storage controller coupled to a storage array comprising one or more storage devices receive a request to write data to one of the storage devices. The storage controller determines a first data block on the storage device comprising a list of deallocated data blocks on the storage device, the list comprising a block number of each deallocated data block and an access operation count value at which each deallocated data block was deallocated. The storage controller identifies a second data block from the list of deallocated data blocks on the storage device based on a corresponding access operation count value from the list and writes the data to the second data block.

Abstract: Processing an I/O operation may include the host selecting one of the available paths over which to send each I/O operation to the data storage system. The selected path may be to a particular director that has responsibility for cache slot allocation and locally accessing the cache slot predicted to include the data of the I/O operation. The host may understand the cache slot allocation algorithm used on the data storage system and how cache slots are allocated for particular logical devices and tracks or locations on the logical devices. The host may direct I/Os down a path to a particular director that has, or will allocate, the cache slot used for the I/Os. There may be multiple directors in a data storage system including a distributed global memory. Each director may locally access a group of cache slots and communicate over a fabric to access the distributed global memory.

Abstract: According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The memory module is operable in at least a second mode and a first mode. The memory module in the second mode is configured to perform training related to one or more training sequences initiated by the memory controller while the memory module is not accessed by the memory controller for memory read or write operations. The memory module in the first mode is configured to perform one or more memory read or write operations not associated with the one or more training sequences by communicating data signals with the memory module. The memory module has an open-drain output pin via which the memory module output a signal indicating a parity error having occurred while the memory module is performing a normal memory read or write operation, and via which the memory module output a signal related to the one or more training sequences.