Abstract: The wait relations among N tasks in a multiprocessing, multiprogramming CPU environment are conformed to a vector of N+1 fields recording which tasks in a system are active and upon what other task any given task directly waits. The vector may be stored in a global register. Positions 1 through N are assigned to the N tasks such that a value p in position r means that task r is waiting directly on task p. One value j of the possible values 0,1,2, . . . , N+1 is designated to indicate an active task. Position j always shows the value j. Without loss of generality and to facilitate the discussion j is assumed to be 0. Thus, the value 0 in register position r means that task r is not waiting and position 0 always has the value 0.The presence of any deadlocks (closures) among the wait relations can always be detected by the computing system by making repeated translations of the vector fields within and upon themselves in no more than log.sub.2 (N+1) iterations. In this regard, log.sub.

Abstract: An input-output subsystem for the handling of data-transfer operations in a digital data processing system. The I/O subsystem provides a series of I/O controller-processors, designated as Line Control Processors, which are organized into groups to form a Base Module. A plurality of such Base Modules are organized to work with a main system interface unit called an Input-Output Translator which is part of the main host system comprising a processor and main memory. The Input-Output Translator (IOT) provides direct memory transfers to and from any connected Line Control Processor independently of the main processor. This arrangement simplifies the expansion of system capability for handling a greater number of peripheral devices on a simple economic basis while increasing data-transfer rates and reducing access errors in individual transfer operations.

Abstract: An address converter according to the present invention is provided with an adddress conversion table, and can store a single logical address, a single physical address, a plurality of logical addresses or a plurality of physical addresses in the same address position, wherein the stored logical address and the stored physical address can be reversibly converted. The address conversion is carried out in such a manner that when the given address is a logical address, the logical address corresponds to one physical address or a plurality of physical addresses read from the address conversion table; and, when the given address is a physical address, the physical address corresponds to one logical address or a plurality of logical addresses read from the address conversion table.

Abstract: A read only memory character generator system for generating dot print characters of a given font within a nine-column-by-nine-row dot matrix comprising a read only memory having a storage capacity of one byte per row of memory, the memory having a first memory means, a second memory means and a third memory means with the first memory means having nine memory row locations of memory storage devices for each character of the font to be printed, the memory storage devices at each successive row for each character being burned in pursuant to the dot matrix pattern for successive columns of dots of not more than eight rows for that given column of that given character, the second memory means having one memory row location of memory storage devices for each character of the font to be printed with the storage devices at each location being burned in pursuant to the dot matrix pattern of the remaining columns of the ninth row dot matrix pattern for not more than six columns of dots for the ninth row of one of sai

Abstract: Described is an interactive enquiry system in which a complete data base is contained at a host computer. Local terminal sub-systems are remotely connected to the host with each local sub-system containing a local data base. Each local data base is dynamically maintained so that the most frequently used pages are retained in local storage. If storage space needs to be created, the least frequently used pages are discarded from the local data base.

Abstract: A unique method of operating a multiprogrammed computing system by dynamically regulating central processing unit (CPU) and/or peripheral resource access such that the parallel processing capability, i.e., thruput of the computing system, is increased and/or such that all programs efficiently share the computing system. The embodiment selected is dependent upon the complexity of the computing system and the amount of computing capability available for regulation. In one embodiment CPU and peripheral access is regulated in an unlike manner. In another embodiment the solution of a dynamic linear programming model, that describes the current resource requirements of two or more of the programs operating in the system, is used to regulate resource access. In yet another embodiment, the system is shared while minimizing the degradation of degradable resources.

Abstract: Device for providing communication between a radiation detector array and a general purpose computer and to receive accumulated scintillation counts from the array of detectors and deposit the same in computer memory in a manner which minimizes subsequent data manipulation.

Abstract: Automatic means and methods for hyphenating words suitable for use with digitally controlled printing apparatus wherein the consonant-vowel pattern of a predetermined selected portion of a word is converted to binary digital values and compared to a compact table of consonant-vowel pattern values. Certain exception conditions may be separately handled to increase accuracy.

Abstract: Disclosed is a device which can utilize, as an input signal, the solution to mathematical problems from an analog computer or which can be used directly with a process that is governed by a mathematical problem to pictorially depict the solution to the problem. The problem being solved can be dynamically displayed on a device such as a conventional television receiver for use by a student, technician or the like. The input signal indicative of the solution of the mathematical problem is fed to a memory and control device which can store the same for subsequent use. The memory also has stored therein data representative of the images necessary to create the pictorial representation of the problem. A programmable device, preferably in the form of a digital computer, interprets the input signals and directs the data in the memory so that it is properly displayed on the television receiver.

Abstract: A distributed computing system has a data exchange processor which is especially adapted to control operations involving the transfer of data among components of the distributed computing system, whereby the master computer is spared the task of controlling data transfer operations.

Abstract: A programmer unit which is connected to the keyboard of a machine is capable of storing, as a program, the sequential occurance of key closures, and of supplying simulated key closures through the keyboard to the machine in the order in which such key closures were initially generated and stored. The programmer enters that key closure information into a storage register. The programmer includes a main control circuit which is responsive to various inputs supplied thereto for also entering control information into the storage register. A register control circuit is responsive to instructions from the main control circuit for entering this information into the correct position within the storage register. When the stored program is accessed, the register control circuit is responsive to instructions from the main control circuit for transmitting key closure information from the storage register in the order in which such information was originally stored.

Abstract: A programmable electronic calculator is provided having an LED display device and a single-step key for causing display and execution of individual steps of a program stored in the calculator, and for causing display of the results of said execution by means of a single actuation of the single-step key. As the key is depressed, the next program step that is to be executed is displayed, together with the number of that step in the program. When the key is released, the program step is executed and the result is displayed.

Abstract: Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms.

Abstract: A minicomputer comprises a microprogrammable central processing unit wherein micro-instruction execution speed is optimized through the use of variable micro-instruction timing logic and by grouping micro-instruction according to execution time. Furthermore, data paths are arranged so that micro-routines that implement more complex operations, i.e., memory reference instructions, follow the fastest route possible. When micro-instructions requiring longer data paths are programmed, the computer dynamically varies the length of the microcycle to be a function of both the type of micro-instruction to be executed and the state of the minicomputer when the micro-instruction is to be executed. A microprogrammable processor port is provided to allow coupling of external hardware, e.g., I/O devices, other processors, etc., directly to the microprogrammed control processor.

Abstract: Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table.

Abstract: A method and apparatus for recording utility meter readings is disclosed. The apparatus includes a solid state memory and an input/output unit which, among other things, causes meter location and identification information to be written into memory, and data representing the respective meter readings to be read out of the memory unit into a central processing unit. A keyboard is utilized to introduce meter readings into the memory and to control the addressing of the memory as each of a plurality of meters is located, identified and the data displayed thereon entered into memory. A visual display unit displays the location of the meter to be read, the meter identification and the meter reading entered via the keyboard. A comparator circuit within the recorder compares the meter reading with expected predetermined maximum and minimum limits for the meter reading and generates an indicator signal to the display when the meter reading does not fall within the predetermined bounds.

Abstract: A read-only memory, adapted to be addressed by the operation code portion of a computer instruction word, stores at addressable locations therein a flag indicating whether a particular combination of operation code bits is a valid combination.

Abstract: An information retrieval system for providing a retrievable updateable display of a permanent microfilm record comprises a gas panel display means capable of providing a composite visual display and microfilm record projection means capable of retrievably providing an image of a selected permanent microfilm record to the gas panel display means from a plurality of such permanent microfilm records. The composite visual display comprises a projection of the selected retrievable permanent microfilm record together with a substantially simultaneous gas panel display of retrievable updateable digital memory stored information which visually supplants predetermined portions of the selectably retrieved projected permanent microfilm record in the composite visual display. The system is controlled by a condition responsive process controller means.

Abstract: A multiple path input/output switching circuit particularly adapted for use with a serially accessed content addressable memory where the switching circuit embodies logical circuitry for implementing a plurality of control and data transfer functions to enhance the communication between the memory and a host system.

Abstract: A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch.