Abstract: A data encoding keyboard for use in electronic processing systems such as electronic calculators includes a pushbutton encoded thumbwheel switch. A plurality of cams secured to the switch define different codes in accordance with the angular orientation of the thumbwheel. The cams engage contacts on a printed circuit matrix adjacent the thumbwheel when the thumbwheel is depressed.

Abstract: A small lightweight hand-held data processing terminal is provided with several visible field display registers, one entry register, and a keyboard. When used by a route salesman, for example, the salesman initially enters information from the keyboard into the entry register, and then upon verifying that the information is accurate the salesman shifts the information up to the individual field registers which might for example relate to product code information, the number of units which are being purchased or sold, the type of transaction whether it is cash, check, credit card, or the like, and other desired information. The transaction information is initially entered in the entry register and is then shifted up to the appropriate field register. Finally, the customer identification number is entered in the entry register, the entire transactional entry is rechecked visually, and then entered into storage.

Abstract: Method and apparatus for updating system variables in least significant bit increments during the period between the times the data are normally sampled. In this manner, a smooth transition from one data level to another is achieved rather than a choppy transition at sampling iteration rates.

Abstract: This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.

Abstract: An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions.

Abstract: An interface adaptor couples peripheral equipment to a bidirectional data bus and an address bus of a digital system. A plurality of interrupt sources are provided on such an interface adaptor circuit. A status bit in a status register of the interface adaptor is provided which contains a logical state indicative of a logical ORing of the plurality of interrupt sources on the interface adaptor circuit.

Abstract: A programmable controller includes a controller processor which operates in response to a control program to transfer command words stored in a data table to an input/output image table in the controller memory. An input/output scanner circuit operates asynchronously with respect to the controller processor to couple command words in the output image table to one or more of a plurality of word-oriented I/O modules and to couple command words from an I/O module to the input image table. A pulse module is described for receiving such command words and controlling the operation of a stepping motor and an analog output module is described which converts a digital number in such command words to an analog output signal.

Abstract: A disk drive includes a first memory for storing microcoded program routines and sub-routines for the drive. One of the routines is a main program routine that is comprised of a plurality of service routines executable in sequence during a respective plurality of time-slots of the main program routine processing cycle. One of the service routines includes a plurality of service sub-routines executable in sequence with only one being executed during each processing cycle. The drive also includes a second memory having a register therein respectively associated with said one service routine. The register is capable of storing the addresses of locations in the first memory at which program instructions for said one service routine are stored.

Abstract: A data processing display system comprises a display device capable of displaying a desired image and including a plurality of points each capable of being selectively illuminated. A main memory storage device is also included in the system and comprises a plurality of addressable storage locations, each location capable of storing a multi-bit display word therein. At least some of the addressable storage locations include in the aggregate a number of bits at least equal to the plurality of points of the display device. A display bit map of the desired image is thus capable of being stored and defined in the at least some addressable storage locations.

Abstract: An exerciser is provided for use with a disk drive of the type having a microprocessor, a first memory for storing microcoded control programs for the drive, a second memory for storing instructions for the head carriage servo control apparatus, an address bus for supplying address signals from the microprocessor to the first and second memories, and a data bus for supplying program instructions from the first memory to the microprocessor, and for supplying instructions from the second memory to the servo control apparatus. The exerciser developes track address signals that are supplied onto the data bus for application to the microprocessor. A third memory is included in the exerciser for storing diagnostic programs. A decoder is also included for decoding an address signal on the address bus in order to generate a new address signal for the third memory. Program instructions accessed from the third memory are supplied onto the data bus for application to the microprocessor.

Abstract: A data processing apparatus for processing digital data in accordance with a plurality of predetermined tasks of preassigned priority values and identified by a respective plurality of devices connected to the data processing apparatus. Each device is capable of generating the respective task request signal when requiring service by the data processing apparatus.

Abstract: A single bit recycling microprocessor which performs sequential and combinational logic equations. The microprocessor has exclusive input and output instructions and performs three basic logic operations, two of which are performed concurrently on each data input. The processor substitutes read only memory (ROM) for a network of logic gates, multiplexers, decoders, flip-flops and counters. The simulation of J-K flip-flops is accomplished by a tandem operation of two R-S flip-flops.

Abstract: A method and means for implementing the control structure of a computer comprising, for example the basic constructs of repetition, conditional execution, and nesting whereby, at any point, a machine language program can be decompiled into the English language source that produced it. The program is loaded into the memory of the machine in a manner to be location independent, so that each segment of a program may be debugged individually, if necessary, without affecting the balance of the program.

Abstract: A velocity control apparatus for a disk drive of the type comprising a recording disk rotatable about its axis, an electromagnetic read/write head for reading data from and writing data onto tracks on a surface of the disk, and means coupled to the head and responsive to velocity command signals for controlling the direction and speed of movement of the head. The velocity control apparatus includes a memory divided into a plurality of sections respectively associated with different ranges of desired distances to be traveled by the head, each section containing a predetermined number of addressable storage locations together defining an approximation of a desired velocity trajectory curve for a desired distance to be traveled included within the range associated with said section.

Abstract: A display unit useful for displaying graphical information and specifically for composing items to be printed on a page. The display unit includes a dot matrix screen and a display memory for storing the information to be displayed. An addressing register identifies memory locations in a sequence starting at location established by a begin display register. The starting location is transferred to the addressing register each time the display unit reaches a first dot location in the display unit. If the starting location is changed, an image corresponding to the item stored in the memory moves on the screen as a unit. Two or more memories can be interconnected to enable a relative motion between images corresponding to the items stored in each display memory.

Abstract: A microprogrammable data communications preprocessor exercises detailed control over a multiplicity of data lines communicating with a microprogrammable central processor while requiring central processor attention on a message basis only. Further minimization of central processor intervention is achieved through a direct memory access channel which permits data transfer directly from the preprocessor to the main memory of the central processor. The preprocessor also includes a line adapter associated with each data communications line for interface purposes, a scratch pad memory for storing data line parameters, and a microprogrammable serial byte microprocessor. Operational speed is enhanced through the inclusion of automatic operation logic which effectively by-passes the serial byte microprocessor for an automatic transfer of two bytes of data.

Abstract: A digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunctioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subsequently addressed.

Abstract: In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit. Page tables are set up in memory containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit can locate its assigned page table, and page table words therein are combined with other control words to access paged memory locations.In one mode of operation an extended addressing mechanism is provided which allows the generation of absolute addresses of paged memory locations having an address field larger than the address field of the control words used to access such paged memory locations.

Abstract: Circuit for receiving service request signals from peripheral devices in a computer system and providing an address to the computer to effect a program transfer to an appropriate service subroutine. An interrupt request signal is generated to cause the computer to jump to a subroutine. A DMA (direct memory access) request is used to store the address at which the proper subroutine is stored. The proper subroutine depends on the highest priority device supplying a service request signal and on the status of that device. Provision is also made for storing a double-length address.

Abstract: An electronic process control system including a digital computer, a computer interface that is easily replaceable in order to change computer types; a logic module for grouping the computer and controller signals and converting between digital and analog representations; and a control unit interface for generating analog signals for a control unit in response to computer commands and adapting the analog control unit to communicate with a digital computer.