Abstract: A magnetic bubble memory system controller is provided to interface a user system and a magnetic domain chip. The controller will functionally accept commands from a user system and deliver those same commands to the appropriate devices associated with the magnetic bubble memory. A further function of the controller device will be to enable multipage read and write functions within the major loop of a magnetic bubble memory chip organization.

Abstract: Macroinstructions stored in a program memory MP of a data processor, read out succesively under the control of a program counter PC, are decoded in a control unit CN which establishes a macroroutine for the transfer and processing of data within the processor as well as between the latter and associated peripheral units. The control unit comprises a microinstruction memory MM addressed by a microinstruction counter CC which is supplied with a starting address from an address store MI at the beginning of any microroutine as determined by a decoding of the final microinstruction of the immediately preceding microroutine. The address store contains 16 groups of 8 cells each; a logic network RL.sub.1, responsive to various bit combinations from a primary decoder DC.sub.1 and a secondary decoder DC.sub.2 in an output circuit of microinstruction memory MM, selects one of the cells of a group activated by a multiplexer MT.sub.

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device.

Abstract: A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

Abstract: A portable electronic dictionary with a micro-computer in a hand-held housing which mounts a plurality of alpha-numeric displays and a keyboard. A plug-in ROM stores a plurality of pairs of sequences of alpha-numeric characters and is searched by a central processing unit in the micro-computer under instructions stored as firmware in another ROM forming part of the micro-computer. One sequence of each stored pair is compared with a sequence which is entered into the keyboard and stored in a RAM also forming part of the micro-computer until a match is found. After one or more sequences have been entered into the keyboard and locations of matching pairs stored in the micro-computer RAM, the pairs of stored sequences can be rolled across the display. Either sequence of each pair can be compared with a sequence entered into the keyboard.

Abstract: A buffer storage system having divisible data storage space which is time-shared by a plurality of external data devices and is accessed by at least two independently clocked bidirectional access ports. The storage system is modular and comprises a variable number of fixed-sized buffer cells, each of which may be associatively addressed by any of the access ports. The transfer of data is at a clock rate determined by the particular accessing port; and the transfer is performed serially to achieve variable field length capability and a reduction in hardware. The amount of total storage space can be easily varied by changing the physical number of buffer cells in the buffer system.

Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.

Abstract: A circuit for sequencing microinstruction sequences in data processing equipment in which during the course of a primary sequence subroutine jumps are performed and subsequences are carried out and at the end of each, a return jump into the primary sequence takes place due to the control provided by a temporarily stored return jump address at a point in the sequence at which a two-part branching instruction is to be evaluated. The first part of the branching instruction characterizes a branching function which is to be carried out dependent on a decision which is specified in the second part thereof. The circuit includes a microinstruction storage from which microinstruction sequences are taken over depending upon the output signals from a central fixed-cycle control circuit fed into a microinstruction register and a recoder which is arranged thereafter.

Abstract: A character-serial electronic digital computer utilizing four character vocabulary, each character being represented by two binary bits, is structured to process character-serial data arriving at the computer in a manner specified and initiated by the arriving data. Data structures that may represent program or operations to be performed on data arriving at the computer input are stored in the computer's storage area in the form of nested data structures that may be illustrated as tree structures in which each node of the tree structure represents an operation. Data structures that may represent operands are also supplied to the computer in a nested organization. This operand data addresses a certain node or operation resident in the computer storage area. The linking up of the arriving operand data with its program data triggers execution of the operation.

Abstract: A character-serial electronic digital computer utilizing a four character vocabulary, each character being represented by two binary bits, is structured to process character-serial data arriving at the computer in a manner specified and initiated by the arriving data. Data structures that may represent program or operations to be performed on data arriving at the computer input are stored in the computer's storage area in the form of nested data structures that may be illustrated as tree structures in which each node of the tree structure represents an operation. Data structures that may represent operands are also supplied to the computer in a nested organization. This operand data addresses a certain node or operation resident in the computer storage area. The linking up of the arriving operand data with its program data triggers execution of the operation.

Abstract: A character-serial electronic digital computer utilizing a four character vocabulary, each character being represented by two binary bits, is structured to process character-serial data arriving at the computer in a manner specified and initiated by the arriving data. Data structures that may represent program or operations to be performed on data arriving at the computer input are stored in the computer's storage area in the form of nested data structures that may be illustrated as tree structures in which each node of the tree structure represents an operation. Data structures that may represent operands are also supplied to the computer in a nested organization. This operand data addresses a certain node or operation resident in the computer storage area. The linking up of the arriving operand data with its program data triggers execution of the operation.

Abstract: A method and apparatus for increasing access speed in a random access memory comprising the utilization of a prefetch register for receiving and temporarily storing a first address portion representing the location of a group of words stored in memory. The first address portion is subsequently utilized to access memory to retrieve a group of words to be stored in memory output registers; a second address portion is utilized to select words contained in the output registers of the memory. Several second address portions may address the various words stored in the output registers of the memory while the first address portion remains the same.

Abstract: An organization for a single chip calculator/controller which reduces the number of interconnections necessary in an integrated circuit chip. The single chip calculator/controller comprises an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. The calculator/controller system also includes data clocking and input/output means. The centralization of the logic functions in the ALU allows any instruction to act upon the data contents of any active storage element.

Abstract: A multiple path input/output switching circuit particularly adapted for use with a serially accessed content addressable memory where several simultaneous data transfers may be carried out between the memory and a host system.

Abstract: The multiplex data processing system comprises a plurality of data processing units connected to form a non-hierachical structure, a shared memory device commonly used by the plurality of data processing units and a job registration unit accessable to the shared memory device for causing the plurality of data processing units to execute their interrupting services. The job registration unit includes circuit means for storing a plurality of job service requests for judging the order of priority of the job service requests, for generating an address signal, and for generating a read/write signal and interruption signal. The shared memory device comprises destructive reading memory cells, a circuit for judging the order of priority of the job service request sent from the job registration unit and the job service request transmitted from the data processing units, and a circuit controlling the READ/WRITE signals sent from the job registration unit and the data processing units.

Abstract: An electronic typographic apparatus includes a multiline display. Coded typographic data for characters of various widths is stored in a character memory, the dot format for the display of characters in different scan lines being produced upon application of stored character data to character generating read only memories. The data entry position of the data entry line of the display is stored and new data is entered into the character memory with counting circuits being employed to keep track of the data entry line and position. The display is "rolled up" one line upon receipt of a carriage return signal, and in the backspacing function, stored data is deleted. The characters are displayed with proportional widths, as a function of an asynchronous pulsed stepping signal generated from a read only memory instantaneously responsive to coded signals of the character memory just prior to the display of elements of a character.

Abstract: The disclosure describes a floating-priority storage access control arrangement for plural processors to a shared main storage in a multi-processing (MP) system. The shared main storage logically couples the main storage units provided with each of the processors into a single expanse of real addresses available to each processor. Exclusive access to the shared storage is given to any processor for as long as that processor can provide a burst of one or more successive storage requests. The burst ends when that processor misses a storage cycle by not providing a locally granted request.The shared storage access is controlled in each processor by means of an MP priority pointer circuit which receives storage requests granted by a local priority circuit in the processor. The MP priority pointer circuits are interconnected between the processors.

Abstract: Herein described is an information retrieval system for identifying and retrieving recorded information from a mass storage system for use in a central processing system. The described system is an associative crosspoint processor system having an input which communicates with and receives stored information from the mass storage system (e.g. magnetic tape, magnetic or optical disk, etc.) upon command from the central processing system. In the system a key momory stores key words which are then compared with data words stored in the mass storage system.

Abstract: A microprogrammable control unit to be associated with a memory in which there have been pre-recorded two sequences of micro-instructions relating to two faces (digital systems) to be coupled and to outside resources adapted to emit control signals necessary for these two digital systems is provided. The control unit comprises at least an addressing unit for the memory adapted to the quasi-simultaneous operation of the two sequences, internal resources comprising at least for each face an input register, an output register of data and a counter and common to the two faces a multiplexer of the signals indicating the states of the internal resources and of the external resources, instruction registers for memorizing codes furnished by the micro-instruction extracted from the memory and a transcoding device controlling the resources, the addressing unit and the multiplexer as a function of the codes of micro-instructions with which data are associated.

Abstract: A data transfer control system for controlling the priority use of a common bus shared by a plurality of data processors which comprises a bus rank memory for storing signals denoting a demand for the priority use of the common bus which are supplied from said plural data processors; and a priority-detecting circuit for detecting the sequential priority positions of signals demanding the priority use of the common bus which are stored in said bus rank memory, wherein the plural data processors are supplied with a control signal instructing the use of the common bus or a waiting position for said use according to the sequential priority positions of the common bus use-demanding signals which have been detected by said priority-detecting circuit.