Abstract: A portable data entry device wholly contained within a small housing and for the manual entry of numerical and code data which can be conveyed to a remote data processor upon command. The device includes an electronic memory capable of storing a plurality of multiple character records and includes manually operable controls for sequencing through the memory for review and updating of previously entered data. A connector is provided on the housing by which the device can be directly connected to a data system for the readout of the stored data. The device is self powered and contains circuitry operative to conserve available energizing power.

Abstract: A data processing system having at least one memory module and at least one data accessing control unit, wherein the data accessing control unit provides a first memory control signal for requesting a start of a memory module and a second memory control signal for preventing a start thereof. Each memory module includes means responsive to the first and second memory control signals and to a busy signal generated by the module, for starting the module when the state of the busy signal indicates the module is not currently in operation and the state of the second memory control signal indicates the module is not to be prevented from starting.

Abstract: The keyboard, printer and recording means are peripheral units under the control of a microprocessor including a programmable read-only memory from which appropriate control instructions are derived. Control signal sequences for operating the word processing system are the result of addressing of the read-only memory in accordance with the sensed status of the attached peripheral units and a priority schedule. The peripheral units operate semiautomatically in response to control instructions to execute a commanded function.Control instructions fall into various classes for controlling peripherals, determining the status of peripherals or performing internal operations within the microprocessor. The format of the next address or sequence of addresses to be applied to the read-only memory is dependent on the class of the prior control instruction or the response of a peripheral unit to a particular control signal.

Abstract: A disk drive comprises a housing having a door through which a cartridge including a recording disk therein may be inserted. A spindle drive assembly is mounted in the housing and is responsive to a first set of instructions for rotating the recording disk of a disk cartridge loaded into the housing through the door and onto the spindle drive assembly. An actuator is also mounted in the housing and is capable of controlled reciprocal movements relative to the axis of rotation of the spindle drive assembly. A head carriage assembly is mounted in the housing to the actuator and includes at least one electromagnetic read/write head thereon for reading data from the writing data onto tracks of the recording disk of a cartridge loaded onto the spindle drive assembly. Servo control apparatus is mounted in the housing and is responsive to a second set of instructions for controlling the speed and direction of the reciprocal movements of the actuator.

Abstract: A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: An apparatus for performing multiple operations during a memory revolution in an electronic dynamic shift register. The memory is initially arranged by the input of control codes such as record, operation, separator, and hold flags. The separator flag defines a normal section and an alternate section, and the operation and hold flags define the position of the next character to be addressed in each of the sections. The record flag is the operating point for an output operation in the normal section. When one of the sections is addressed and it does not contain the operation flag, the hold and operation flags are exchanged in order that the operation flag is in the section addressed. With the operation flag in the normal section, an input zone is defined by the separator flag in the alternate section, and a revision zone is defined from the record flag to the separator flag in the normal section.

Abstract: A programmable controller module (PCM) for operably coupling a plurality of peripheral devices (PDs) of various communication disciplines to a data processor (DP) or to remote PCMs through a serial interface adapter (SIA) or parallel interface adapter (PIA). The PCM is comprised of a special purpose computer having a program of subroutines arranged in memory modules which define and implement specific communication protocols (routines) for different communication disciplines. Each PD connected to a PCM by an SIA or PIA is assigned a channel code and is addressed by channel code. A discipline identification (DID) line is connected from each adapter channel to one of a predetermined number of terminals in the PCM. There is one terminal for each communication discipline for which there is stored in a memory module an appropriate protocol. Each channel has its DID line connected to the appropriate terminal according to the communication discipline of the PD connected to it.

Abstract: In a large scale data processing system employing partitioning, paging and segmentation techniques with a descriptor enforced access to storage areas, a method and apparatus for testing address formulation is disclosed. All fundamental steps in address preparation are preserved whether a single step formulation is possible, as when the page table words are present in associative memory, or a multiple step process is required, as when the page table words must be retrieved from main memory.

Abstract: The disclosure describes an improved apparatus for simultaneously transferring data or commands between several peripheral devices and a central processing unit. The apparatus includes a peripheral control unit which links the central processing unit to several peripheral devices. The peripheral control unit operates as a master with respect to the central processing unit and the peripheral devices in order to increase the capacity of the central processing unit.

Abstract: Pattern information for production of a Jacquard pattern by a knitting or a weaving machine is automatically and quickly obtained. A pattern drawn on a sheet by a designer is converted to an analog type electrical signal by a television camera, and said analog signal is converted to a digital signal according to each color of each picture element. Said digital signal is stored in a digital memory. After the edition of said digital signal in the memory, the digital signal which defines the color of each picture element is applied to a knitting or a weaving machine.

Abstract: A system for arranging the memory in an electronic dynamic shift register for performing multiple operations during a memory revolution. Control codes, such as separator and record flags, are input into the shift register memory for defining an input and a revision zone. Upon detecting these control codes during a memory revolution, data codes are input into the input and revision zones and deleted from the revision zone. Another control code, such as a page end code, input into the revision zone defines an output zone. During an output operation data codes in the output zone are output from the record flag through the page end code.

Abstract: A calculator system having a transparent keyboard includes an apparatus for electronically labeling the keyboard by displaying alphanumeric symbols through the keyboard. The apparatus comprises a keyboard selection device and a liquid crystal keyboard display device having a predetermined number of display planes each containing preselected symbols. The keyboard selection device operates both as a selection device and as an annunciator-feedback device, for selecting the symbols or legends of a given plane to label or configure the keyboard, and for feeding back to a user of the system the status of the selection device when it is activated. An alternative embodiment of the invention utilizes light-emitting diodes (LED's) for labeling the keyboard.

Abstract: A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction.

Abstract: A communication control unit useful for operably coupling a plurality of peripheral devices to a data processing system including a central processing unit (CPU) and a main system memory. The communication control unit is comprised of three major sections: (1) A direct memory access module (DMA) for communicating with the memory of the CPU; (2) A serial interface adaptor module (SIA) for converting parallel data to serial data for transmission to a peripheral device and serial data to parallel data on receiving from a peripheral device; and (3) A programmable controller module (PCM) connected between the DMA and SIA for providing the overall control of message reception and transmission. The PCM comprises a small special-purpose programmable parallel computer. A program (firmware) stored in a read-only memory of the PCM enables the PCM to handle the different communication disciplines observed by various peripheral devices operable with the communication control unit.

Abstract: An adaptable programmable calculator employs modular read-write and read-only memories separately expandable to provide additional program and data storage functions within the calculator oriented toward the environment of the user, and an LSI NMOS central processing unit, capable of handling sixteen-bit parallel binary operations, binary-coded-decimal arithmetic, sixteen-bit parallel input/output operations, two-level interrupt from up to sixteen input/output devices, and a direct memory access channel.

Abstract: A plurality of trap save areas are linked to form a pool of such areas from which an area may be loaded with context from various sources in response to a trap condition, such as the addressing of unuseable memory, the loaded area unlinked from the pool, and various pointers changed to reflect such unlinking. The unlinked area is associated with the process which was executing at the time of the occurrence of the trap condition by effectively being coupled to the interrupt level of such process. Independent of the interrupt level, a trap handler routine, specific to the nature of the trap condition, is executed following which the unlinked area is returned to the pool and the various pointers changed to reflect such return.

Abstract: A digital processor which may be used in a calculator or the like is provided by an MOS/LSI semiconductor chip which contains a ROM or read-only-memory for storing instructions, a bit-parallel arithmetic unit for operating on data stored in a random access memory and control circuitry for defining the operation of the system. The control circuitry includes a programmable logic array for decoding instruction words. Space on the chip is saved by a time-shared decoder which forms part of the programmable logic array and also decodes addresses for the ROM.

Abstract: A multi-speed ECG magnetic tape scanning device for processing and observing in a relatively short interval of time large quantities of ECG signals from two pairs of ECG leads. The ECG information is recorded on a miniature recorder which the patient carries to record the information for a long period of time, such as 24 hours. The recorder includes a built-in clock with a visible display. The recorder also includes an event marker, which is activated by the patient when the patient experiences an event. The play-back of the ECG information is in real time or at multiple high speed play-back speeds of 30, 60 and 120 times real time. During play-back at high speed, a multi-speed multi-channel paper writer reproduces analog trend data, digital printed data and event marking. The trend information is usually heart rate and ST segment level, so as to produce a scanning of an entire 24 hour information tape in as short a period as 12 minutes.

Abstract: The invention relates to a computer in which control means provide for high speed context switching. In a more specific aspect, the invention involves an arithmetic unit in which a workspace pointer register and control means operable on an interrupt store the contents of the workspace pointer in an element of a workspace in memory designated by the interrupt program and store in the workspace pointer register the address of the first element of the interrupt program workspace.A first register stores the address of a first element of a set of dedicated workspace elements in main memory.A second register stores the memory address of a current instruction of a problem program.