Abstract: A method for substituting one memory module for another, faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called, and responds to the address of the faulty module whenever the latter is called.

Abstract: The described embodiment provides storage control (PSCF) for overlapping the handling of processor store requests between their generation by an instruction execution means (IPPF) and their presentation to system main storage (MS).The embodiment uses a store counter, an inpointer counter, an outpointer counter, a translator pointer register, an output counter and a plurality of registers sets to process and control the sequencing of all store requests so that the PSCF can output them to MS in the order received from the IPPF. The embodiment uses the counters to coordinate the varying delays in PSCF processing of plural store request contained in different register sets and the translator.The store counter obtains independence between plural IPPF operand address (OA) registers which send the store requests and plural PSCF register sets which handle the store request. The number of OA registers is made independent of the number of register sets.

Abstract: A data processing system includes a disk drive, a disk drive controller, a main memory and a CPU. The main memory has disk command data stored therein in a chain of disk command blocks (DCB's). Each DCB contains a first word pointing to the next DCB in the chain, a second word containing status information and a third word containing command information. A portion of the command word contains a predetermined verification word when the DCB is valid. The CPU includes means for comparing this portion with the predetermined verification word as stored in a constant memory. If the two correspond, the DCB is valid. Each DCB also includes a fourth word pointing to a block of main memory in which header data is stored. Header data defines the address of the recording location of the disk. A fifth word points to a block of main memory in which label data is stored.

Abstract: A raster typ display apparatus includes interlaced even-and-odd frames. A digital memory of a computer stores line segment data in locations which are sequentially read out to form a line segment display with overlapping line segments. The first line of one field is defined by a "0" start location and a third removed location for the end. The second line is defined by the fourth and seventh locations, and so forth. The first line of the second field starts with the last data taken plus two to access and define the line by the second and fifth locations, and so forth. The first field again reads the start to third locations, fourth to seventh, etc. Data points equal to twice the scan lines are displayed with each scan line spread over four data points. An off-scale detector prevents a line segment directly between the data points and creates a pair of line segments at the top and bottom of the display screen. An extended line from a break point in a curve to screen bottom is also prevented.

Abstract: The system comprises a central information processing unit, an input/output unit, a first-in first-out stack which is connected to receive information from the central information processing unit for sending a "FULL" signal to the central information processing unit when the stack is filled with the information sent from the central information processing unit and for sending thereto an "EMPTY" signal when the stack is empty, an input/output control circuit which operates to transfer the information from the first-in first-out stack to the input/output unit and to detect the state thereof for sending a "READY" signal to the central processing unit when the input/output unit is in a state ready for accepting the information, a command register coupled to the central information processing unit to be set at a particular bit by a bit signal sent from the central processing unit when it receives the "FULL" signal from the first-in first-out stack and the "READY" signal from the input/output control circuit, and a

Abstract: A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode.

Abstract: A system for producing signals for proportional display of characters on a display device. The system utilizes a memory means for storing codes for a text and means for sequencing through the memory. The output of the memory which addresses (1) a character dot generator ROM and (2) a character width defining ROM. A shift register receives parallel inputs from the dot generator ROM and delivers a sequence of output levels to control the intensity of a display oscilloscope beam. Another shift register receives parallel inputs from the character width ROM (2) one input at a time, so that its output pulse occurs after the writing of the character is finished. Means is provided for applying the pulse output of the parallel input shift register to advance the character memory means to the next character to be displayed.

Abstract: An automated library circulation control system includes a plurality of remote book processing terminals and a computer controlling the terminals and processing data between the terminals and the computer to maintain a current inventory of the circulation status of the library books. The system provides for automatic charging of library materials by patrons, record keeping of all library transactions, modification and interrogation of computer data files, intercommunication between the computer and a remote data processor and detection of unauthorized removal of books from the library. Each terminal has a card reader for patron identification, an optical reader for book identification, an electromagnetic activator for magnetizing and demagnetizing a magnetic strip in each book, a printer for printing charge-out information, and a display screen and keyboard for communications between patron and computer.

Abstract: Data relating to the attitude and spin rate of a spacecraft is stored in a data storage system located at an earth station in communication with the spacecraft. Leading and trailing edges of the data, usually in the form of pulses, received from sensors suitably mounted on the spacecraft, address locations in a random access memory (RAM) into which the count accumulated in a counter is written. At the end of each group of pulses, referred to as a frame, data relating to the status of the pulses received from the spacecraft is also loaded into the random access memory. Simultaneously, a computer is signalled that a complete frame of data has been loaded in the random access memory. The computer then generates address and other signals such that the data can be read out of memory and thereby allow the computer to calculate the attitude and spin rate of the spacecraft.

Abstract: Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate.

Abstract: A structure for an easily testable single chip calculator/controller comprising an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. Two test pins are provided, one placed in the input bus and the other placed in the output bus. The test pins are placed in the test mode by the application of a TEST signal to their terminals. Signals from the test pins will be routed to outside diagnostic or testing equipment.

Abstract: A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.

Abstract: A portable data entry device wholly contained within a small housing and for the manual entry of numerical and code data which can be conveyed to a remote data processor upon command. The device includes an electronic memory capable of storing a plurality of multiple character records and includes manually operable controls for sequencing through the memory for review and updating of previously entered data. A connector is provided on the housing by which the device can be directly connected to a data system for the readout of the stored data. The device is self powered and contains circuitry operative to conserve available energizing power.

Abstract: A system for remotely controlling the printing of data supplied by a central processing unit at a plurality of printers is disclosed having a central processing unit for addressing which printers are to print the data and for transmitting the data to be printed over a transmission channel to the printers, each printer having an address matcher to check if it is the printer being addressed and a latching circuit for conditioning the printer to receive and print data if it is one of the printers which is addressed. This circuit allows a plurality of printers to be addressed and requires only one transmission by the central processing unit of the data to the printers.

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series.

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series.

Abstract: A data recording and readback subsystem for digital computer systems employing random access electron beam memories having an electron beam write/read apparatus for recording data to be stored on a recording member that is subject to fatigue in the eventuality of excessive write/read storage operations at any given physical location on the recording member. The improved method and apparatus for data management comprising systematically permuting the physical location of data stored on the recording member, recording each permutation of the data, deriving signals representative of the number of permutation operations, and combining programmer initiated requests from the computer system central processing unit for data stored in the electron beam memory with the signals representative of the number of permutations to derive an actual physical address signal for application to the electron beam memory for recovery of the requested data.

Abstract: A system for replacing obsolete postal rate data with new data used by a remote mail processing apparatus comprises a central data processor for generating the new data. An encoder translates the new data into electronic tone signals which are transmitted to the remote apparatus by, for example, telephone transmission lines. The electronic tone signals are translated back into new data by a decoder. A memory incorporated in the remote apparatus is equipped to store obsolete or new data at a plurality of storage locations and a programming transfer controller, which interconnects the decoder and memory, sequentially addresses each of the locations storing obsolete data, erases the obsolete data, and loads new data into the addressed location.

Abstract: An automatic alternator for a priority circuit comprises one or more flip-flop circuits connected to the channels of the priority circuit by a plurality of AND gate means which are responsive to outputs of the flip-flop circuits and of the priority circuit channels to alternate the servicing of successive simultaneous signals at two or more requesting ports. The flip-flop circuit input is connected to the requesting ports through an AND gate and changes its operating state in response to the presence of two simultaneous signals at the requesting ports and to a cyclically occurring clock input to the flip-flop circuit. When the operating state of the flip-flop circuit is changed to the alternating mode, the signal at the requesting port served by the priority circuit channel during the preceding cycle is blocked from that channel and another request signal appearing simultaneously at the remaining port or ports is applied to the other channel or channels.

Abstract: A multi-speed ECG magnetic tape scanning device for processing and observing in a relatively short interval of time large quantities of ECG signals from two pairs of ECG leads. The ECG information is recorded on a miniature recorder which the patient carries to record the information for a long period of time, such as 24 hours. The recorder includes a built-in clock with a visible display. The recorder also includes an event marker, which is activated by the patient when the patient experiences an event. The play-back of the ECG information is in real time or at multiple high speed play-back speeds of 30, 60 and 120 times real time. During play-back at high speed, a multi-speed multi-channel paper writer reproduces analog trend data, digital printed data and event marking. The trend information is usually heart rate and ST segment level, so as to produce a scanning of an entire 24 hour information tape in as short a period as 12 minutes.