Patents Examined by Mark Prenty
  • Patent number: 10249638
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Yamashita, Tamotsu Ogata, Masamichi Fujito, Tomoya Saito
  • Patent number: 10249605
    Abstract: An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kuchanuri Subhash, Rastogi Sidharth, Deepak Sharma, Chul-hong Park, Jae-seok Yang
  • Patent number: 10249623
    Abstract: A semiconductor integrated circuit includes semiconductor substrate having a plurality of first potential side areas, including a first two adjacent first potential side areas, each first potential side area having a high potential side circuit, a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate, a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, penetrating the first semiconductor region in a depth direction, a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region. Each of the first two adjacent first potential side areas includes a first side area facing the other, each first side area includes the third semiconductor region, and is free of the second semiconductor region.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: April 2, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide Tanaka
  • Patent number: 10242940
    Abstract: A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface and a second surface opposite the first surface. The electrical connection is on the first surface of the redistribution structure. The encapsulant encapsulates the first surface of the redistribution structure and the electrical connection. A portion of the electrical connection is exposed by the encapsulant.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: March 26, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jung-Liang Yeh, Meng-Jen Wang, Tsung-Yueh Tsai, Chih-Ming Hung
  • Patent number: 10230020
    Abstract: Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 12, 2019
    Assignee: eLux Inc.
    Inventors: Kenji Alexander Sasaki, Paul J. Schuele, Mark Albert Crowder
  • Patent number: 10221064
    Abstract: A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 5, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Lawrence Prestousa Natan, Adrian Arcedera, Roveluz Lledo-Reyes, Sarah Christine-Sanchez Torrefranca
  • Patent number: 10217750
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Patent number: 10211333
    Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 19, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Madhur Bobde, Sik Lui
  • Patent number: 10211149
    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Moo Harr, Kyung Seob Oh, Hyoung Joon Kim
  • Patent number: 10211201
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 10204834
    Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yeon-Cheol Heo
  • Patent number: 10205088
    Abstract: A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element; a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 12, 2019
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa, Atsushi Tsumita
  • Patent number: 10205036
    Abstract: An array of Geiger-mode avalanche photodiodes is formed in a die and includes: an internal dielectric structure, arranged on the die; and an external dielectric region arranged on the internal dielectric structure. The external dielectric region is formed by an external material that absorbs radiation having a wavelength that falls in a stop-band with low wavelength and transmits radiation having a wavelength that falls in a pass-band with high wavelength, at least part of the pass-band including wavelengths in the infrared. The internal dielectric structure is formed by one or more internal materials that substantially transmit radiation having a wavelength that falls in the stop-band and in the pass-band and have refractive indices that fall in an interval having an amplitude of 0.4. In the stop-band and in the pass-band the external dielectric region has a refractive index with the real part that falls in the above interval.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Piero Fallica, Salvatore Lombardo
  • Patent number: 10199291
    Abstract: A semiconductor arrangement is presented.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Riegler, Angelika Koprowski, Mathias Plappert, Frank Wolter
  • Patent number: 10192969
    Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid Hafez, Hsu-Yu Chang, Roman Olac-Vaw, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu, Neville Dias
  • Patent number: 10193064
    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
  • Patent number: 10186534
    Abstract: The present invention is related to a multi full-well pixel for a metal-oxide-semiconductor (MOS) active pixel image sensor. It is further related to a MOS active pixel image sensor comprising a plurality of such pixels. The invention is particularly related to active pixel image sensors realized in complementary MOS (CMOS) technology. According to the invention, a MOS capacitor is used as a switchable capacitor, wherein the gate electrode is connected to the voltage that is to be read out. Semiconductor-side contacts of the MOS capacitor are used to apply a switching control signal that allows the effective capacitance of the MOS capacitor to be selected and being radiation-hard for damaging X-ray radiation.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 22, 2019
    Assignee: TELEDYNE DALSA B.V.
    Inventor: Willem Hendrik Maes
  • Patent number: 10186599
    Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, Andrew M. Greene, Sean Lian, Balasubramanian Pranatharthiharan, Mark V. Raymond, Ruilong Xie
  • Patent number: 10177169
    Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10177100
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a passive component attached to the active surface of the semiconductor chip, an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, the first connection member and the second connection member each including at least one redistribution layer electrically connected to the connection pads of the semiconductor chip, and the passive component being electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Il Kim, Mi Jin Choi