Patents Examined by Mark Prenty
  • Patent number: 10109626
    Abstract: To provide a semiconductor device having an element isolation structure formed in the main surface of a semiconductor substrate, having a space in a trench, and prevented from having deteriorated performance due to an increase in the height of the top portion of the space. A trench portion is formed in the main surface of a semiconductor substrate by using a hard-mask insulating film. A first insulating film that covers the upper surface of the hard-mask insulating film and the surface of the trench portion is formed, followed by etch-back of the first insulating film to expose the upper surface of the hard-mask insulating film. Then, second and third insulating films that cover the upper surface of the hard-mask insulating film and the surface of the trench portion are formed to form a space in the trench portion.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 23, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Masaaki Shinohara
  • Patent number: 10109714
    Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Tek Po Rinus Lee
  • Patent number: 10103155
    Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kohei Sakaike, Toshiyuki Iwamoto, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Satoshi Nagashima, Koichi Sakata, Yuta Watanabe
  • Patent number: 10103198
    Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 16, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Saori Kashiwada, Yuichi Ohsawa, Daisuke Saida, Chikayoshi Kamata, Kazutaka Ikegami, Megumi Yakabe, Hiroaki Maekawa
  • Patent number: 10090321
    Abstract: An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. A level difference is formed in a side surface of the contact, a portion of a region of the side surface other than the level difference contacts the insulating film. The insulating member contacts the level difference.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shingo Nakajima
  • Patent number: 10068935
    Abstract: A CMOS image sensor pixel (200) comprising a photosensitive element (101) for generating a charge in response to incident light; a plurality of charge storage elements (103); a plurality of transfer gates (102) for enabling the transfer of charge between the photosensitive element and an associated one of the charge storage elements; and one or more first electrical connections (201) for placing at least two of the plurality of charge storage elements in mutual electrical contact.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 4, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Daniel Gaebler, Xuezhou Cao
  • Patent number: 10068980
    Abstract: A method of forming a gate structure with a modified gate geometry, including, forming two gate spacers and a dummy gate fill on a channel, wherein the dummy gate fill is between the two gate spacers, forming a stressed layer on the two gate spacers, wherein the stressed layer is on the surfaces of the gate spacers opposite the dummy gate fill, and wherein the stressed layer applies a tensile stress to the two gate spacers, and removing a portion of the dummy gate fill, wherein the tensile stress applied to the two gate spacers is no longer balanced by the dummy gate fill, such that each of the two gate spacers becomes inclined at an obtuse angle relative to a top surface of the remaining dummy gate fill.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10056309
    Abstract: Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a semiconductor chip and exposed from a main surface of a sealing body located on a front surface side of the semiconductor chip. Each of the first and second semiconductor devices includes a collector terminal electrically connected with a back surface electrode of the semiconductor chip and exposed from the main surface of the sealing body located on a back surface side of the semiconductor chip. The collector terminal of the first semiconductor device is electrically connected with the emitter terminal of the second semiconductor device via a conductor pattern formed on an upper surface of the substrate.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Akira Muto
  • Patent number: 10038032
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Toshiyuki Sasaki
  • Patent number: 10029910
    Abstract: Structures and formation methods of a MEMS device structure are provided. The MEMS device structure includes a semiconductor substrate having a first region and a second region, and a MEMS layer over the semiconductor substrate. The MEMS layer has a first through hole positioned in the first region and a second through hole positioned in the second region. The MEMS device structure also includes a cap layer over the MEMS layer, a first cavity between the semiconductor substrate and the cap layer and in the first region, and a second cavity between the semiconductor substrate and the cap layer and in the second region. The MEMS device structure further includes a carbon-based degradation product in the first cavity.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu
  • Patent number: 10008666
    Abstract: Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: June 26, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hans S Cho, Janice H Nickel, R. Stanley Williams, Jaesung Roh, Jinwon Park, Choi Hyejung, Moonsig Joo, Jiwon Moon, Changgoo Lee, Yongsun Sohn, Jeongtae Kim
  • Patent number: 10008491
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Robert J. Gauthier, Jr., Souvick Mitra, Mickey Yu
  • Patent number: 9997523
    Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Toshiro Nakanishi, Donghwan Kim, Suhwan Kim, Yubin Kim, Jin Soak Kim, Gabjin Nam, Sungkweon Baek, Taehyun An, Eunae Chung
  • Patent number: 9997465
    Abstract: Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACUTURING CO., LTD.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9991365
    Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xuefeng Liu, Peng Xu, Yongan Xu
  • Patent number: 9991308
    Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong Jae Lee, Oh Kyum Kwon, Myoung Kyu Park
  • Patent number: 9985134
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 9975755
    Abstract: A microelectromechanical system includes a membrane of amorphous carbon having a thickness between 1 nm and 50 nm, and for example between 3 nm and 20 nm.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 22, 2018
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Anne Ghis, Marc Delaunay
  • Patent number: 9978894
    Abstract: The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 22, 2018
    Inventor: Robbie J. Jorgenson
  • Patent number: 9978905
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1?wN, and at least one barrier layer comprising InbGa1?bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1?wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1?bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen