Patents Examined by Mark Prenty
  • Patent number: 9978753
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 9960174
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuo Ohashi, Masaaki Higuchi
  • Patent number: 9960184
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
  • Patent number: 9953894
    Abstract: A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second surface located opposite the first surface, a metal species provided on the second surface, and a plated metal portion provided at least in part on the second surface on the metal species. The semiconductor device further includes a first region where the plated metal portion is provided and a second region where the plated metal portion is not provided are alternately arranged at a peripheral portion of the second surface.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shingo Masuko, Yoshiharu Takada, Kazuo Fujimura
  • Patent number: 9954098
    Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes at least a substrate, an isolated structure, a gate, a source, a drain, a deep well, and a body well. The deep well extends under the isolated structure, and the body well is formed in the deep well between the gate and the isolated structure, wherein the body well has a convex region extending under the isolated structure. The deep well has a drive-in region outside the convex region of the body well, and the drive-in region has a lower doping concentration than remainder of the deep well.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 24, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yu-Jui Chang
  • Patent number: 9947689
    Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9947650
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 17, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 9941124
    Abstract: A semiconductor device includes a semiconductor base body having a first main surface and a second main surface, the first main surface and the second main surface being opposite with each other; a Schottky electrode that is disposed on the first main surface and forms a Schottky junction with the semiconductor base body; and a barrier metal layer that is brought into ohmic contact with the first main surface around the Schottky electrode and covers a side surface of the Schottky electrode.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 10, 2018
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Hiromichi Kumakura, Tomonori Hotate, Hiroko Kawaguchi, Hiroshi Shikauchi, Ryohei Baba, Yuki Tanaka
  • Patent number: 9941350
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 10, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Hongning Yang, Ronghua Zhu, Jiang-Kai Zuo
  • Patent number: 9932221
    Abstract: A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 3, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Lawrence Prestousa Natan, Adrian Arcedera, Roveluz Lledo-Reyes, Sarah Christine-Sanchez Torrefranca
  • Patent number: 9923039
    Abstract: A display device includes a substrate and first, second and third thin film transistor. The first thin film transistor is disposed over the substrate, and includes a first gate electrode which has a first transmittance. The second thin film transistor is disposed over the substrate, and includes a second gate electrode which has a second transmittance substantially different from the first transmittance. The third thin film transistor is disposed over the substrate, and includes a third gate electrode which has a third transmittance substantially different from the first transmittance.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Wan Ahn, Yong-Jae Jang
  • Patent number: 9917053
    Abstract: A semiconductor device includes a semiconductor layer comprising an upper surface and a recess through the upper surface and including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface at an upper edge, an insulating member in the lower part of the recess, an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on a portion of the semiconductor layer adjacent to the upper edge of the recess, and an electrode on the insulating member and the portion of the insulating film covering the upper edge of the recess. The first portion of the insulating film is thinner than thicknesses of each of the second and third portions thereof.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Ishikawa
  • Patent number: 9917179
    Abstract: A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bot
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9899365
    Abstract: A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen
  • Patent number: 9899544
    Abstract: An array of Geiger-mode avalanche photodiodes is formed in a die and includes: an internal dielectric structure, arranged on the die; and an external dielectric region arranged on the internal dielectric structure. The external dielectric region is formed by an external material that absorbs radiation having a wavelength that falls in a stop-band with low wavelength and transmits radiation having a wavelength that falls in a pass-band with high wavelength, at least part of the pass-band including wavelengths in the infrared. The internal dielectric structure is formed by one or more internal materials that substantially transmit radiation having a wavelength that falls in the stop-band and in the pass-band and have refractive indices that fall in an interval having an amplitude of 0.4. In the stop-band and in the pass-band the external dielectric region has a refractive index with the real part that falls in the above interval.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Piero Fallica, Salvatore Lombardo
  • Patent number: 9881912
    Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units, and each of the circuit units includes, a first electrode, a second electrode; a first switching element and a second switching element electrically connected in series between the first electrode and the second electrode, and a third electrode electrically connected between the first switching element and the second switching element. The circuit units are arranged in an annular shape.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 30, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuto Takao, Shinya Kyogoku
  • Patent number: 9865606
    Abstract: According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chika Tanaka, Daisuke Matsushita
  • Patent number: 9862593
    Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 9, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Peter Smeys, Jong Il Shin, Jongwoo Shin
  • Patent number: 9865801
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a fixed layer that includes a magnetic material overlying a substrate. A non-magnetic first tunnel barrier layer is formed overlying the fixed layer. A total free layer is formed overlying the first tunnel barrier layer, where the total free layer includes a first spacer layer between first and second free layers. The first free layer includes one or more of cobalt, iron, and boron. The first spacer layer is non-magnetic and includes a first spacer layer boron sink material that has a boride formation enthalpy lower than the boride formation enthalpy of cobalt.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kazutaka Yamane, Vinayak Bharat Naik, Kangho Lee
  • Patent number: 9859364
    Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a top interlayer dielectric (ILD), a contact, and an isolation pillar. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The top ILD is disposed on the gate structure. The contact is disposed on the source/drain feature. The contact includes a barrier metal and a contact metal. The barrier metal is disposed on and in contact with the source/drain feature. The contact metal is disposed on the barrier metal. The isolation pillar is disposed adjacent to the contact. The isolation pillar is in contact with the barrier metal and the contact metal of the contact and the top ILD.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Hsiung Wang, Bao-Ru Young, Tung-Heng Hsieh