Abstract: A low gate resistance high-k metal gate transistor device is formed by providing a set of gate stacks (e.g., replacement metal gate (RMG) stacks) in a trench on a silicon substrate. The gate stacks in the trench may have various layers such as: a high-k layer formed over the substrate; a barrier layer (formed over the high-k layer; a p-type work function (pWF) layer formed over the barrier layer; and an n-type work function (nWF) layer formed over the pWF layer. The nWF layer will be subjected to a nitrogen containing plasma treatment to form a nitridized nWF layer on the top surface, and an Al containing layer will then be applied over the gas plasma treated layer. By utilizing a gas plasma treatment, the gap within the trench may remain wider, and thus allow for improved Al fill and reflow at high temperature (400° C.-480° C.) subsequently applied thereto.

Abstract: A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween.

Abstract: A memory cell is provided that includes a semiconductor pillar and a reversible resistance-switching element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region includes a first proportion of germanium greater than a proportion of germanium in the top region and/or the bottom region. The reversible resistivity-switching element includes a material selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.

Abstract: Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.

Abstract: A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed.

Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.

Abstract: This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Abstract: In one embodiment, electrostatic discharge (ESD) devices are disclosed.

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Abstract: An encapsulation structure for silicon pressure sensor including a case and a stem is proposed. The case and the stem are connected with a cavity therebetween. A sealing pad and a pressure sensitive silicon chip are provided in the said cavity. The sealing pad is placed under the silicon chip and the silicon chip is connected to the external circuit through the bonding pad. This invention, with the anti-overloading ability, simplifies the encapsulation structure and manufacturing process which greatly reduces the cost of material and process.

Abstract: A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa.

Abstract: Optoelectronic devices, materials, and associated methods having increased operating performance are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material, a first doped region in the semiconductor material, a second doped region in the semiconductor material forming a junction with the first doped region, and a laser processed region associated with the junction. The laser processed region is positioned to interact with electromagnetic radiation. Additionally, at least a portion of a region of laser damage from the laser processed region has been removed such that the optoelectronic device has an open circuit voltage of from about 500 mV to about 800 mV.

Abstract: Disclosed are a GaN-based compound power semiconductor device and a manufacturing method thereof, in which on a GaN power semiconductor element, a contact pad is formed for flip-chip bonding, and a bonding pad of a module substrate to be mounted with the GaN power semiconductor element is formed with a bump so as to modularize an individual semiconductor element. In the disclosed GaN-based compound power semiconductor device, an AlGaN HEMT element is flip-chip bonded to the substrate, so that heat generated from the element can be efficiently radiated.

Abstract: When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film (8T) is formed. A first electrode (12) is formed on the first side of the silicon carbide substrate (SB) at the element region (CL). A second electrode (14) is formed on a second side of the silicon carbide substrate (SB).

Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract: A monolithic metal oxide semiconductor field effect transistor (MOSFET)-Schottky diode device including a chip, a MOSFET, a Schottky diode and a termination structure is provided. The chip is divided into a transistor region, a diode region and a termination region. The MOSFET is disposed on the transistor region. The Schottky diode is disposed on the diode region. The termination structure is disposed on the termination region. The transistor region and the diode region are divided by the termination region. The MOSFET and Schottky diode share the termination structure.

Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.

Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.