Patents Examined by Mark Prenty
  • Patent number: 9281439
    Abstract: A nitride semiconductor element 1 includes a base structure part 5, and an element structure part 11 formed on the base structure part 5 and having at least an n-type AlGaN based semiconductor layer 6, and p-type AlGaN based semiconductor layers 8, 9, 10, and further includes an n-electrode contact part 13a formed on the n-type AlGaN based semiconductor layer 6, an n-electrode pad part 13b formed on the n-electrode contact part 13a, and a p-electrode 12 formed on the p-type AlGaN based semiconductor layers 8, 9, 10, in which an AlN mole fraction in the n-type AlGaN based semiconductor layer 6 is 20% or more, the n-electrode contact part 13a includes one or more metal layers, and the p-electrode 12 and the n-electrode pad part 13b have a common laminated structure of two or more layers having an Au layer as an uppermost layer, and an Au diffusion preventing layer composed of conductive metal oxide and formed under the uppermost layer to prevent Au diffusion.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 8, 2016
    Assignee: Soko Kagaku Co., Ltd.
    Inventors: Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 9276206
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Eng Huat Toh
  • Patent number: 9276176
    Abstract: A light-emitting device comprises: a light-emitting stack having an active layer; a transparent insulating layer on the light-emitting stack; and an electrode structure having a first electrode on the transparent insulating layer; wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack, the refractive index of the transparent insulating layer is between 1 and 3.4 both inclusive, and the transmittance of the transparent insulating layer is greater than 80%.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 1, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Hung-Ta Cheng, Yao-Ru Chang, Shih-I Chen, Chia-Liang Hsu
  • Patent number: 9269849
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 23, 2016
    Assignee: First Solar, Inc.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Patent number: 9263558
    Abstract: A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction. An insulator layer is upon one side the base layer and emitter region. Base and emitter electrodes are isolated from each other by the insulator layer and electrically contact the base layer and emitter region through the insulator layer. A thin and flexible collector layer is upon an opposite side of the base layer. A microcavity is formed in the collector layer and is aligned with the emitter region. Collector electrodes are arranged to sustain a microplasma within the microcavity with application of voltage to the collector electrodes. A depth of the emitter region and a thickness of the base layer are set to define a predetermined thin portion of the base layer as a base region between the emitter region and the microcavity. Microplasma generated in the microcavity serves as a collector.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: February 16, 2016
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Paul A. Tchertchian, Clark J. Wagner, Dane J. Sievers, Thomas J. Houlahan, Benben Li
  • Patent number: 9263262
    Abstract: The invention relates to nanowires which consist of or comprise semiconductor materials and are used for applications in photovoltaics and electronics and to a method for the production thereof. The nanowires are characterized in that they are obtained by a novel method using novel precursors. The precursors represent compounds, or mixtures of compounds, each having at least one direct Si—Si and/or Ge—Si and/or Ge—Ge bond, the substituents of which consist of halogen and/or hydrogen, and in the composition of which the atomic ratio of substituent:metalloid atoms is at least 1:1.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 16, 2016
    Assignee: Spawnt Private S.à.r.l.
    Inventors: Norbert Auner, Christian Bauch, Rumen Deltschew, Sven Holl, Javad Mohsseni, Gerd Lippold
  • Patent number: 9263695
    Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Shunpei Yamazaki, Takahiro Ishisone
  • Patent number: 9246057
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 26, 2016
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Patent number: 9236563
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element having a structure in which a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a third magnetic layer are stacked, wherein the third magnetic layer comprises a first region and a plurality of second regions, and each of the second regions is surrounded by the first region, has conductivity, and has a greater magnetic property than the first region.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 12, 2016
    Inventors: Yutaka Hashimoto, Tadashi Kai, Masahiko Nakayama, Hiroaki Yoda, Toshihiko Nagase, Masatoshi Yoshikawa, Yasuyuki Sonoda
  • Patent number: 9236569
    Abstract: A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Funai Electric Co., Ltd.
    Inventors: Shigeo Furuta, Yuichiro Masuda, Tsuyoshi Takahashi, Masatoshi Ono, Yutaka Hayashi, Taro Itaya, Yasuhisa Naitoh, Tetsuo Shimizu
  • Patent number: 9231196
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The element includes a lower electrode, a stacked body provided on the lower electrode and including a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The first magnetic layer is under the tunnel barrier layer, the second magnetic layer is on the tunnel barrier layer. The first magnetic layer includes a first region and a second region outside the first region to surround the first region. The second region includes an element in the first region and other element being different from the element.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 5, 2016
    Inventors: Kuniaki Sugiura, Tadashi Kai
  • Patent number: 9224821
    Abstract: In one example, a customizable nonlinear electrical device includes a first conductive layer, a second conductive layer, and a thin film metal-oxide layer sandwiched between the first conductive layer and the second conductive layer to form a first rectifying interface between the metal-oxide layer and the first conductive layer and a second rectifying interface between the metal-oxide layer and the second conductive layer. The metal-oxide layer includes an electrically conductive mixture of co-existing metal and metal oxides. A method forming a nonlinear electrical device is also provided.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 29, 2015
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Minxian Max Zhang, Jianhua Yang, Gilberto Medeiros Ribeiro, R. Stanley Williams
  • Patent number: 9214488
    Abstract: According to one embodiment, a solid state imaging device includes a semiconductor substrate comprising a first surface and a second surface opposite the first surface; a circuit at a side of the first surface of the semiconductor substrate; a pixel in the semiconductor substrate and converting light from a side of the second surface into electric charge; and an element at a side of the second surface of the semiconductor substrate. The pixel includes a photo diode in the semiconductor substrate at the side of the first surface, and the photo diode includes a diffusion layer in an impurity region in the semiconductor substrate at the side of the first surface.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ikuko Inoue
  • Patent number: 9214626
    Abstract: A resistance change memory device with a high ON/OFF radio can be provided according to an embodiment includes a first electrode containing a first element, a resistance change layer provided on the first electrode and containing an oxide of the first element, an oxygen conductive layer provided on the resistance change layer, containing a second element and oxygen, having oxygen ion conductivity, and having a relative permittivity higher than a relative permittivity of the resistance change layer, and a second electrode provided on the oxygen conductive layer. The resistance change layer undergoes dielectric breakdown earlier than the oxygen conductive layer when a voltage between the first electrode and the second electrode is continuously increased from zero.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 15, 2015
    Assignees: TOKYO INSTITUTE OF TECHNOLOGY, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki Kakushima, Chunmeng Dou, Parhat Ahmet, Hiroshi Iwai, Yoshinori Kataoka
  • Patent number: 9209387
    Abstract: A phase change memory and its fabrication method are provided. A bottom electrode structure is provided through a substrate. A mask layer is formed on the substrate and the bottom electrode structure. A first opening is formed in the mask layer to expose the bottom electrode structure. A spacer is formed on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode structure. The first opening including the spacer therein has a bottom width less than a top width. A heating layer is formed at least on the surface portion of the bottom electrode structure exposed by the spacer. A phase change layer is formed on the heating layer to completely fill the first opening. A top electrode is formed on the phase change layer and the mask layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 8, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCE
    Inventor: Ying Li
  • Patent number: 9209392
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 9190566
    Abstract: Disclosed is a light emitting device package capable of improving luminous efficiency. The light emitting device includes a substrate; a first buffer layer on the substrate; a first insulating layer on the first buffer layer; a second buffer layer on the first insulating layer; a second insulating layer on the second buffer layer; a third buffer layer around the second buffer layer and the insulating layer; and a light emitting structure on the third buffer layer.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 17, 2015
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Hoon Choi, Young Jae Choi, Ho Jun Lee
  • Patent number: 9184218
    Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Lijie Zhang, Young-Bae Kim, Youn-Seon Kang, In-Gyu Baek, Masayuki Terai
  • Patent number: 9184341
    Abstract: Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). A preferred device is a hybrid plasma semiconductor device having base, emitting and microcavity collector regions formed on a single side of a device layer. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: November 10, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Paul A. Tchertchian, Clark J. Wagner, Dane J. Sievers, Thomas J. Houlahan, Benben Li
  • Patent number: 9171853
    Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-Hyun You, Hyeong Park, Bongtae Park, Jeehoon Han