Abstract: A semiconductor memory device includes a substrate having a cell region and a peripheral region, a gate stack including a plurality of insulating layers and a plurality of gates alternately stacked on the cell region of the substrate, a stress buffer layer on the gate stack, a vertical channel that extends vertically through the gate stack and is electrically connected to the substrate, a memory layer wrapped around the vertical channel. A bit line electrically connected to the vertical channel may be provided on the gate stack. In a method of fabricating a semiconductor device, the buffer stress layer is formed directly on an upper insulating layer of a stack whose shape is altered to form the gate stack to inhibit warping of the substrate during fabrication of the device.

Abstract: A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer is formed using two or more kinds of organic compounds and contains at least the second organic compound.

Abstract: A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block.

Abstract: A non-volatile memory cell and a magnetic field-partitioned non-volatile memory for multi-bit storage are provided. The non-volatile memory cell for multi-bit storage includes a bottom electrode. A resistance-changing memory material covers the bottom electrode. A top electrode including a high-mobility material is disposed on the resistance-changing memory material. The top electrode has two post portions supporting a bar-shaped portion. At least two bits are stored in portions of the resistance-changing memory material connecting to the top electrode when an external magnetic field is applied along different directions.

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes a substrate, a transparent film, and a light-gathering film. The substrate includes organic light emitting diode (OLED) elements. The transparent film is disposed on the substrate. The light-gathering film is disposed on the transparent film. In the fabrication method of the display panel, a substrate is first provided, in which the substrate includes OLED elements. Then, a transparent film is provided, in which the transparent film has a first surface and a second surface opposite to the first surface. Thereafter, a light-gathering material is coated to form a light-gathering film on the first surface of the transparent film. Then, a sensing layer is disposed on the second surface of the transparent film. Thereafter, the transparent film is disposed on the substrate to sandwich the sensing layer between the transparent film and the substrate.

Abstract: A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a magnetoresistive element provided on the substrate. The magnetoresistive element includes a first magnetic layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer or the second magnetic layer includes a first region, second region, and third region whose ratios of crystalline portion are higher in order closer to the tunneling barrier.

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Abstract: A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract: In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.

Abstract: A light-emitting module with improved light extraction efficiency and reliability is provided. In the light-emitting module, an element substrate with gas barrier properties is used; a light-emitting element is optically connected to one surface side of the element substrate; and a diffuse reflection layer is in contact with the other surface side of the element substrate. The diffuse reflection layer has a diffuse reflectance of greater than or equal to 75% and less than 100%. The light-emitting element includes a layer containing a light-emitting organic compound between a pair of light-transmitting electrodes. The element substrate transmits light emitted from the light-emitting element; the refractive index of the element substrate is different from that of layer containing a light-emitting organic compound by 0.2 or less.

Abstract: A brightness enhanced self-luminous type display including a self-luminous display panel and a brightness enhancement stacked layer is provided. The self-luminous display panel includes pixels arranged in array, wherein each pixel includes light-emitting sub-pixels displaying different colors. The brightness enhancement stacked layer is disposed on the self-luminous display panel. The brightness enhancement stacked layer includes an absorptive polarizer layer, a phase retardation layer and a reflective polarizer layer. The reflective polarizer layer is between the self-luminous display panel and the phase retardation layer. The phase retardation layer is between the absorptive polarizer layer and the reflective polarizer layer. The reflective polarizer layer includes reflective polarizer blocks arranged in array.

Abstract: In an image sensor in which each microlens of a microlens array is disposed at a position corresponding to each pixel on a side to which light flux is incident, a layer formed of a member different from a member constituting the microlens array is disposed on the side of the microlens array to which light flux is incident, and a surface of the layer formed of the different member has a phase structure optically-opposite to that of the microlens array.

Abstract: A synthetic antiferromagnet serving as a reference layer for a magnetic tunnel junction is a laminate with a plurality of “x+1” magnetic sub-layers and “x” non-magnetic spacers arranged in an alternating fashion, with a magnetic sub-layer at the top and bottom of the laminated stack. Each spacer has a top and bottom surfaces that interface with adjoining magnetic sub-layers generating antiferromagnetic coupling between the adjoining sub-layers. Perpendicular magnetic anisotropy is induced in each magnetic sub-layer through an interface with a spacer. Thus the dipole field exerted on a free layer is substantially reduced compared with that produced by a conventional synthetic antiferromagnetic reference layer. Magnetic sub-layers are preferably Co while Ru, Rh, or Ir may serve as non-magnetic spacers.

Abstract: According to an embodiment, in a method of fabricating a nonvolatile semiconductor memory device, second trenches penetrating the first and second conductive layers above the first trenches are formed to reach the stack, and a second insulating layer is formed on the second trenches and the first insulating layer so as to fill the second trenches. A part of the second insulating layer in a first region extending in a direction orthogonal to a direction that the first and second semiconductor pillars extend in a plane parallel to the back gate layer is removed while a part of the second insulating layer in a second region adjacent to the first region is left. The first sacrificial layer is selectively removed, and the first conductive layers and second conductive layers exposed in the first and second trenches are silicidized.

Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.

Abstract: A disclosed semiconductor device includes a semiconductor substrate including a first area, a gate electrode formed over the first area of the semiconductor substrate, a first active region formed in the first area of the semiconductor substrate at a lateral side of the gate electrode, a first silicide layer formed at least on a sidewall surface of the gate electrode in the first area, the first silicide layer is electrically connected to the first active region.