Patents Examined by Mark Prenty
  • Patent number: 8878192
    Abstract: A silicon carbide substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type provided on the first layer, and a third layer provided on the second layer and doped with an impurity for providing the first conductivity type. The silicon carbide substrate has a trench formed through the third layer and the second layer to reach the first layer. The first layer has a concentration peak of the impurity in a position away from the trench in the first layer. As a result, a silicon carbide semiconductor device having an electric field relaxation structure that can be readily formed is provided.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: November 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Toru Hiyoshi, Takeyoshi Masuda
  • Patent number: 8878249
    Abstract: A method for growing high mobility, high charge Nitrogen polar (N-polar) or Nitrogen face (In,Al,Ga)N/GaN High Electron Mobility Transistors (HEMTs). The method can provide a successful approach to increase the breakdown voltage and reduce the gate leakage of the N-polar HEMTs, which has great potential to improve the N-polar or N-face HEMTs' high frequency and high power performance.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 4, 2014
    Assignee: The Regents of the University of California
    Inventors: Jing Lu, Stacia Keller, Umesh K. Mishra
  • Patent number: 8871577
    Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon Taek Jeong, Bo Sung Kim, Doo-Hyoung Lee, June Whan Choi, Tae-Young Choi, Kano Masataka
  • Patent number: 8872242
    Abstract: A silicon carbide substrate has a first conductivity type. The silicon carbide substrate has a first surface provided with a first electrode and a second surface provided with first trenches arranged to be spaced from one another. A gate layer covers an inner surface of each of the first trenches. The gate layer has a second conductivity type different from the first conductivity type. A filling portion fills each of the first trenches covered with the gate layer. A second electrode is separated from the gate layer and provided on the second surface of the silicon carbide substrate. A gate electrode is electrically insulated from the silicon carbide substrate and electrically connected to the gate layer. Thereby, a silicon carbide semiconductor device capable of being easily manufactured can be provided.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8853015
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Patent number: 8847283
    Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 30, 2014
    Assignee: Transphorm Japan, Inc.
    Inventors: Youichi Kamada, Kenji Kiuchi
  • Patent number: 8847313
    Abstract: Methods and devices for transparent electronics are disclosed. According to an embodiment, transparent electronics are provided based on transfer printed carbon nanotubes that can be disposed on both rigid and flexible substrates. Methods are provided to enable highly aligned single-walled carbon nanotubes (SWNTs) to be used in transparent electronics for achieving high carrier mobility while using low-temperature processing. According to one method, highly aligned nanotubes can be grown on a first substrate. Then, the aligned nanotubes can be transferred to a rigid or flexible substrate having pre-patterned gate electrodes. Source and drain electrodes can be formed on the transferred nanotubes. The subject devices can be integrated to provide logic gates and analog circuitry for a variety of applications.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 30, 2014
    Assignee: University of Southern California
    Inventors: Chongwu Zhou, Fumiaki Ishikawa, Hsiao-Kang Chang, Koungmin Ryu
  • Patent number: 8836048
    Abstract: A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Josephine B. Chang, Michael P. Chudzik, Martin M. Frank, Michael A. Guillorn, Christian Lavoie, Shreesh Narasimha, Vijay Narayanan
  • Patent number: 8836031
    Abstract: After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, David V. Horak, Charles W. Koburger, III, Shom Ponoth
  • Patent number: 8829529
    Abstract: A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Rumo Satake
  • Patent number: 8823042
    Abstract: An organic light emitting diode (OLED) display including a display panel, a chip on film, and a printed circuit (PCB) is disclosed. In one embodiment, the display panel includes a display area having an OLED and a pixel circuit, and a pad area in an outer side of the display area. The chip on film is connected to the pad area, is bent toward a non-luminescent surface of the display panel, and include an integrated circuit chip. The PCB includes at least a part overlapping with the chip on film in an outer side of the non-luminescent surface of the display panel, and an opening for receiving the integrated circuit.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hak-Gyu Kim
  • Patent number: 8822286
    Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: September 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen, Frank Hui
  • Patent number: 8823026
    Abstract: A nitride-based semiconductor light-emitting device of an embodiment includes a semiconductor multilayer structure having a growing plane which is an m-plane and being made of a GaN-based semiconductor. The semiconductor multilayer structure includes a n-type semiconductor layer, a p-type semiconductor layer, a p-side electrode provided on the p-type semiconductor layer, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer. The ratio of the thickness of the active layer to the thickness of the n-type semiconductor layer, D, is in the range of 1.8×10?4?D?14.1×10?4. The area of the p-side electrode, S, is in the range of 1×102 ?m2?S?9×104 ?m2. A maximum current density which leads to 88% of a maximum of the external quantum efficiency is not less than 2 A/mm2.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Junko Iwanaga, Akira Inoue
  • Patent number: 8816435
    Abstract: Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). Doped solid state semiconductor regions are in a thin flexible solid state substrate, and a flexible non conducting material defining a microcavity adjacent the semiconductor regions. The flexible non conducting material is bonded to the thin flexible solid state substrate, and at least one electrode is arranged with respect to said flexible substrate to generate a plasma in said microcavity, where the plasma will influence or perform a semiconducting function in cooperation with said solid state semiconductor regions. A preferred on-wafer device is formed on a single side of a silicon on insulator wafer and defines the collector (plasma cavity), emitter and base regions on a common side, which provides a simplified and easy to manufacture structure.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 26, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Paul A. Tchertchian, Thomas J. Houlahan, Dane J. Sievers, Benben Li, Clark J. Wagner
  • Patent number: 8816464
    Abstract: The present invention is a photodiode and/or photodiode array, having a p+ diffused area that is smaller than the area of a mounted scintillator crystal, designed and manufactured with improved device characteristics, and more particularly, has relatively low dark current, low capacitance and improved signal-to-noise ratio characteristics. More specifically, the present invention is a photodiode and/or photodiode array that includes a metal shield for reflecting light back into a scintillator crystal, thus allowing for a relatively small p+ diffused area.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 26, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8809891
    Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Hisao Ikeda, Hiroki Ohara, Makoto Hosoba, Junichiro Sakata, Shunichi Ito
  • Patent number: 8803199
    Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 12, 2014
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Paul Bridger, Jianjun Cao
  • Patent number: 8803287
    Abstract: An electronic device comprising a semiconductor structure having an integrated circuit back end capacitor and an integrated circuit back end thin film resistor and a method of manufacturing the same is provided. The semiconductor structure comprises a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. Furthermore, there is a second dielectric layer which is disposed on the bottom plate of the capacitor and on top of the thin film resistor body. A top plate of the capacitor is disposed on the second dielectric layer in a region of the second dielectric layer which is defined by the lateral dimensions of the bottom plate of the capacitor. The bottom plate and the resistor body are laterally spaced apart layers which are both disposed on the first dielectric layer and which are composed of a same thin film material.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Christoph Dirnecker, Berthold Staufer
  • Patent number: 8785263
    Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Young Choi, Bo-Sung Kim
  • Patent number: 8779521
    Abstract: In one preferred form shown in FIGS. 2a to 2c there is provided a field effect transistor (24). The field effect transistor includes an off switch gate (42) and a switch bridge semiconductor (44). The switch bridge (44) is provided for charging the off switch gate (42) such that the off switch gate (42) is able to screen the electric field of the control gate (32) of the field effect transistor.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: July 15, 2014
    Inventor: Dac Thong Bui