Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.

Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.

Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Abstract: A magnetization control element according to an aspect of the invention includes a magnetization control layer containing a magnetoelectric material exhibiting a magnetoelectric effect, and a magnetic coupling layer that is magnetically coupled to a magnetization of a first surface of the magnetization control layer through exchange coupling and exhibits a magnetic state according to the magnetization of the first surface, wherein a magnetization having a component in a direction opposite to a direction of a magnetization of the magnetic coupling layer is imparted to the magnetization control layer.

Abstract: Embedded BEOL memory devices having a top electrode pillar are provided. In one aspect, a method of forming an embedded memory device includes: depositing a first ILD on a substrate; forming first/second interconnect in the first ILD over logic/memory regions of the substrate; depositing a capping layer onto the first ILD; forming a memory film stack on the capping layer; patterning the memory film stack into a memory device(s) including a bottom electrode, a dielectric element, and a top electrode; patterning the top electrode to form a pillar-shaped top electrode; depositing a conformal encapsulation layer over the capping layer and memory device(s); depositing a second ILD over the conformal encapsulation layer; and forming a first metal line(s) in the second ILD in contact with the first interconnect(s), and a second metal line(s) in the second ILD in contact with the pillar-shaped top electrode. A device is also provided.

Abstract: A two-transistor-two-resistor (2T2R) resistive random access memory (ReRAM) structure, and a method for forming the same includes two vertical field effect transistors (VFETs) formed on a substrate, each VFET includes an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape that extend horizontally beyond the channel region. A metal gate material is disposed on and around the channel region. A portion of the metal gate material is located between the two VFETs. A ReRAM stack is deposited within two openings adjacent to a side of each VFET that is opposing the portion of the metal gate material located between the two VFETs. A portion of the epitaxial region in direct contact with the ReRAM stack acts as a bottom electrode for the ReRAM structure.

Abstract: Disclosed is a backside illuminated image sensor and a method of manufacturing the same and, more particularly, a backside illuminated image sensor and a method of manufacturing the same, in which a height difference is between a pixel region and a surrounding region having a boundary between on an uppermost or back surface of a substrate, thereby eliminating one or more problems that occur when a thickness of a color filter in the pixel region is uneven.

Abstract: A memory device may be provided including one or more bottom electrodes, one or more mask elements, one or more top electrodes and a switching layer. The bottom electrode(s) may include a first bottom electrode, the mask element(s) may include a first mask element and the top electrode(s) may include a first top electrode. The first mask element may be arranged over a first part of the first bottom electrode. The first top electrode may be arranged over and in contact with the first mask element. The switching layer may be arranged to extend over a second part of the first bottom electrode, and along a first side surface of the first mask element and further along a first side surface of the first top electrode. The first side surfaces of the first mask element and the first top electrode may face a same direction.

Abstract: A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.

Abstract: A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area.

Abstract: The techniques described herein relate to methods and apparatus for a resistive switching device. The resistive switching device includes a first electrode formed in a substrate. The resistive switching device also includes a plurality of layers formed above the first electrode, including a plurality of oxide layers, wherein one or more of the plurality of oxide layers comprise doped oxide layers, and one or more conductive spacers, wherein each pair of oxide layers of the plurality of oxide layers are separated by a conductive spacer of the one or more conductive spacers. The resistive switching device also includes a second electrode formed above the plurality of layers, such that the first electrode, the plurality of layers, and the second electrode are in series.

Abstract: A semiconductor device comprises a plurality of pillars on a semiconductor substrate, and a support pattern in contact with at least one side surface of each of the pillars. The support pattern connects the pillars with one another. The support pattern includes a plurality of support holes that expose side surfaces of the pillars. The support holes includes a first support hole and a second support hole that are spaced apart from each other. The pillars have circular cross-sections. A ribbon-like hexagon is obtained in a plan view when connecting an inner sidewall of the first support hole with central points of the cross-sections of the pillars exposed through the first support hole.

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.

Abstract: A method for fabricating an integrated circuit is provided. The method includes forming a memory cell over a substrate, wherein the memory cell comprising a top electrode, a bottom electrode, and a resistance switching element between the bottom electrode and the top electrode; forming a dielectric layer over the memory cell and the substrate; etching a via opening in the dielectric layer to expose the top electrode of the memory cell; forming a spacer in the via opening; performing a liner removal process to the dielectric layer after forming the spacer; and forming a conductive feature connected to the top electrode in the via opening.

Abstract: Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.

Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.

Abstract: Present disclosure provides a pixel for receiving an incident light, the pixel including a semiconductor substrate, a photo diode in the semiconductor substrate, and a metasurface structure over the semiconductor substrate. The metasurface structure has a first side and a second side opposite to the first side, the first side of the metasurface structure facing the semiconductor substrate, the second side of the metasurface structure facing the incident light. The metasurface structure includes a plurality of trenches at the second side, wherein the plurality of trenches have a same profile from a cross-sectional view.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.