Patents Examined by Martin H. Edlow
  • Patent number: 5032883
    Abstract: A TFT of the present invention includes a transparent insulative substrate, a gate electrode formed on the substrate, a gate insulating film formed on at least the gate electrode, a semiconductor film formed at a position on the gate insulating film corresponding to the gate electrode, source and drain electrodes arranged on the semiconductor film so as to form a channel portion, a transparent insulating film covering the source and drain electrodes and the semiconductor film, and a transparent electrode connected to the source electrode. A through hole is formed in the transparent insulating film above the source electrode. The transparent electrode is formed on a portion of the transparent insulating film except for a portion above the channel portion on the semiconductor film.
    Type: Grant
    Filed: September 7, 1988
    Date of Patent: July 16, 1991
    Assignee: Casio Computer Co., Ltd.
    Inventors: Haruo Wakai, Nobuyuki Yamamura, Syunichi Sato, Minoru Kanbara
  • Patent number: 5027164
    Abstract: A semiconductor device generally has an anode layer, a first semiconductor layer, a first cladding layer having a superlattice structure, an active layer having a superlattice structure, a second cladding layer having a superlattice structure, a cathode barrier layer, a second semiconductor layer, and a cathode layer. The cathode barrier layer allows electrons to tunnel therethrough when a voltage is applied across the anode and cathode layers so that a potential on a side of the superlattices is positive with respect to the cathode barrier layer. The active layer has the superlattice with a bottom energy of a miniband from which electrons transit to a lower miniband with a light emission which bottom energy is smaller than those of the superlattices of the first and second cladding layers.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: June 25, 1991
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 4959709
    Abstract: The present invention provides a semiconductor memory device comprising a MOSFET (16) and a storage capacity element (15) and performing data writing/reading.The MOSFET (16) is formed on a main surface of a silicon substrate (1) and a storage capacity element (15) is formed on a surface of the reverse side of the silicon substrate (1). The MOSFET (16) comprises source and drain regions (3, 4) formed on the main surface of the silicon substrate (1), a channel region (17) positioned therebetween and a word line forming a gate electrode (9a).
    Type: Grant
    Filed: November 28, 1988
    Date of Patent: September 25, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Jinzo Watanabe
  • Patent number: 4935799
    Abstract: Disclosed is a composite semiconductor device which comprises: a second and a third semiconductor regions of a second conductivity type formed in a first semiconductor region of a first conductivity type independently of each other and so as to be exposed on one main surface of a semiconductor substrate; a fourth and a fifth semiconductor regions of the first conductivity type formed in the second semiconductor region independently of each other and so as to be exposed on the one main surface of the semiconductor substrate; a first insulated gate electrode formed on the second semiconductor region located between the fifth and first semiconductor regions and exposed on the one main surface; a second insulated gate electrode formed on the first semiconductor region located between the second and third semiconductor regions and exposed on the one main surface; an electrode which shorts the fourth and third semiconductor regions; another electrode which shorts the second and fifth semiconductor regions; and a fu
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: June 19, 1990
    Inventors: Mutsuhiro Mori, Tomoyuki Tanaka, Yasumichi Yasuda
  • Patent number: 4933745
    Abstract: A package is provided for a pair of microwave semiconductor devices, such package comprising upper and lower mating covers, each one of such covers having bonded thereto a corresponding one of the pair of microwave semiconductor devices. With such arrangement, after the devices are bonded to the cover to form a component of the package, the effective impedance of the thus formed component is electrically characterized, or measured. Having characterized a large quantity of such components, the components are then sorted into bins with components having substantially matched characteristics being placed in a common one of the bins. Pairs of such components in a common bin are used as the upper and lower cover for the package. Thus, assembly time is significantly reduced since additional matching compensation techniques are not required.
    Type: Grant
    Filed: November 25, 1988
    Date of Patent: June 12, 1990
    Assignee: Raytheon Company
    Inventors: Richard L. O'Shea, Paul J. Bourque
  • Patent number: 4931854
    Abstract: An integrated circuit package utilizing low temperature sealing glass and having reduced lead capacitance. Voids in the glass material on the base substrate and the cap substrate result in the formation of glass-free cavities when the base substrate is fused to the cap substrate. A lead frame extending from and passing through the glass material which couples the base substrate to the cap substrate also passes through the glass-free cavities, resulting in a reduced parasitic capacitance of the package leads.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: June 5, 1990
    Assignee: Kyocera America, Inc.
    Inventors: Hiro Yonemasu, Kiyohide Shirai, Ikunosuke Kawamura
  • Patent number: 4929999
    Abstract: The invention relates to the combination of a support and a semiconductor body and to a method of manufacturing same, in which a deformable metal layer is disposed between the semiconductor body and the support. The semiconductor body is connected to the support by pressing the semiconductor body and the support against each other under pressure after heating the metal layer. The semiconductor body is then provided at its surface facing the support with at least one projecting part, which is embedded in the metal layer.
    Type: Grant
    Filed: April 4, 1989
    Date of Patent: May 29, 1990
    Assignee: U.S. Philips Corporation
    Inventors: Arthur M. E. Hoeberechts, Petrus J. M. Peters
  • Patent number: 4929984
    Abstract: A resonant tunnelling barrier (RTB) structure device (e.g., diode), having a large peak-to-valley current density (Jp/Jv) ratio, includes an InP substrate and a RTB structure structure. The RTB structure is formed by a first doped layer of InP or In.sub.0.53 GA.sub.0.47 As, a first barrier layer of Al.sub.x Ga.sub.1-x As.sub.y Sb.sub.1-y (0.ltoreq.x.ltoreq.1, y=0.51+0.05x), a well layer of InP or In.sub.z Ga.sub.1-z As (0.52.ltoreq.z.ltoreq.0.54), a second barrier layer of the AlGaAsSb, and a second doped layer of InP or In.sub.z Ga.sub.1-z As. The layers of the RTB structure are lattice-matched to InP.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: May 29, 1990
    Assignee: Fujitsu Limited
    Inventors: Shunichi Muto, Tsuguo Inata, Atsushi Takeuchi, Yoshihiro Sugiyama
  • Patent number: 4929987
    Abstract: A wafer with a <100> orientation comprises N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorus ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: May 29, 1990
    Assignee: General Instrument Corporation
    Inventor: Willem G. Einthoven
  • Patent number: 4928157
    Abstract: A protection diode structure for a MOS transistor which includes a semiconductor substrate layer and a gate electrode insulated from the semiconductor substrate layer and in which a driving voltage is applied therebetween to create an inversion layer in an operating mode, includes a first semiconductor layer, a second semiconductor layer formed in the first semiconductor layer and connected to the gate electrode, and a third semiconductor layer formed to surround the first semiconductor layer, uniformly separated from the second layer, and connected to the semiconductor substrate layer, wherein the first and second semiconductor layers constitute a first diode having a breakdown voltage greater than the driving voltage and less than the gate withstand voltage of the MOS transistor, and the first and third semiconductor layers constitute a second diode having a breakdown voltage less than the gate withstand voltage of the MOS transistor.
    Type: Grant
    Filed: April 5, 1989
    Date of Patent: May 22, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Takashi Kimura
  • Patent number: 4924289
    Abstract: A semiconductor device having an air bridge wiring structure comprising a first layer of conductors disposed on a semiconductor substrate, a plurality of bridges posts disposed on widened portions of the first layer of conductors, and bridge plates disposed straddling a plurality of bridge posts, the widened portions of the first layer of conductors being disposed at positions which are not in straight lines but are shifted with respect to each other.
    Type: Grant
    Filed: June 17, 1988
    Date of Patent: May 8, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Matsuoka
  • Patent number: 4924294
    Abstract: In a multi-chip module, a structure for selectively connecting two conductors. A switchable connector (36) is disposed between a first and second portion (30,32) of a copper conductor (28). The switchable connector comprises an amorphous silicon layer (58), which extends between two spacer pads (56) that are electrically connected to the first and second portions of the copper conductor. A barrier layer (60) is formed atop the amorphous silicon, physically separating it from a reactive metal layer (62). The reactive metal layer is coated with an antireflective coating (64). Interaction of the reactive metal layer with the amorphous silicon layer is prevented by the barrier layer until the barrier layer is heated above C. A laser beam (66) is focused on opposite edges of the switchable connector, causing the barrier layer and reactive metal layer to diffuse into the amorphous silicon, forming electrically conductive silicides.
    Type: Grant
    Filed: March 1, 1989
    Date of Patent: May 8, 1990
    Assignee: The Boeing Company
    Inventor: Minas H. Tanielian
  • Patent number: 4924288
    Abstract: A high current gain high-frequency planar process PNP transistor comprising an emitter region and a surrounding annular collector. The surface of the transistor is covered with an insulative oxide layer, with an aperture to the emitter region. An overlaying metal layer is provided which substantially covers the base region between the emitter and collector. Connection to the emitter region is provided with an extension of the metal surface to the aperture. However except for this connection, the surface area above the emitter region is not covered by the metal layer. The resulting transistor provides a high-frequency PNP transistor with significantly enhanced Beta.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: May 8, 1990
    Assignee: Unitrode Corporation
    Inventor: Robert A. Neidorff
  • Patent number: 4924285
    Abstract: An integrated, planar, single-channel, photodetector-amplifier device is disclosed. The single-channel device includes a photodetector layer and an amplifier layer above the photodetector layer. The photodetector layer is low-doped to give a low dark current and is sufficiently thick to give a high quantum efficiency. The amplifier layer is of a smaller thickness and is a more highly doped material than the photodetector layer, to provide an amplifier having high gain. An insulating layer is included between the photodetector and amplifier layers for electrically isolating the photodetector and amplifier layers. The layers are fabricated on a substrate. Isolation regions are also included for electrically laterally isolating a photodetector, amplifier, and other circuit components comprising the single channel device from each other.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: May 8, 1990
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Gordon W. Anderson, John B. Boos, Harry B. Dietrich, David I. Ma, Ingham A. G. Mack, Nicolas A. Papanicolaou
  • Patent number: 4922311
    Abstract: A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. There is a conducting layer, termed a window pad layer, over portions of these regions. Because of the insulating top layer and sidewall spacers on the gate, the window may be misaligned with respect to the source and drain regions, and maybe even closer to the gate than are these regions, but electrical contacts to these regions are still obtained. The window pad layer may also be used as sublevel interconnect.
    Type: Grant
    Filed: April 11, 1989
    Date of Patent: May 1, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Kuo-Hua Lee, Chih-Yuan Lu, David S. Yaney
  • Patent number: 4922312
    Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: May 1, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Donald J. Coleman, Roger A. Haken
  • Patent number: 4922218
    Abstract: A photovoltaic device comprises a photoactive layer for generating carriers when light is applied thereto, and a window layer containing at least silicon and hydrogen and provided on the light incidence side of the photoactive layer. Hydrogen concentration in the window layer is higher in the layer's light incidence side than in the side facing the photoactive layer. Thus, the light incidence side of the window layer has a rough surface.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: May 1, 1990
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kaneo Watanabe, Masayuki Iwamoto, Koji Minami
  • Patent number: 4920404
    Abstract: A light-emitting diode is mounted in the bottom of a cavity in a metal lead and the assembly is potted in a transparent plastic material. The walls of the cavity surround the sides of the light-emitting diode in sufficiently close proximity to effectively shield the light-emitting diode from thermal expansion stresses from the plastic potting material which would induce light output degradation. Such a cavity may be a right-circular cylinder with a diameter less than 75 micrometers greater than the largest transverse dimension of the light-emitting diode. The front face of the light-emitting diode may be flush or beneath the face of the metal lead for minimizing stress. The cavity may be deep enough that the front face of the light-emitting diode is closer to the bottom of the cavity than to its open end. The front face may protrude beyond the open end of the cavity and be surrounded by a reflective surface. The edges of the front face of the light-emitting diode may be beveled for minimizing stress.
    Type: Grant
    Filed: May 12, 1989
    Date of Patent: April 24, 1990
    Assignee: Hewlett-Packard Company
    Inventors: Dinesh C. Shrimali, Frank M. Steranka, Cheryl L. McLeod
  • Patent number: 4920395
    Abstract: The sensitivity of a photodiode, which has a semiconductor substrate of first conductivity, an island region of an epitaxial layer of oppposite second conductivity formed on the substrate, a diffused region of the first conductivity formed in the epitaxial layer through its entire thickness so as to define the island region and a diffused region of the second conductivity formed in a surface region of a marginal area of the island region, is enhanced by forming a shallow laminar region of the first conductivity in the surface of a major area of the island region by ion implantation. The photodiode of improved sensitivity can be integrated with simplified circuit components to provide a single-chip photodetecting or photosensitive device by a conventional bipolar process.
    Type: Grant
    Filed: August 23, 1988
    Date of Patent: April 24, 1990
    Assignee: Nissan Motor Company, Limited
    Inventor: Hideo Muro
  • Patent number: RE33209
    Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: May 1, 1990
    Assignee: Board of Trustees of the Leland Stanford Jr. Univ.
    Inventor: James D. Plummer