Patents Examined by Martin H. Edlow
  • Patent number: 4918493
    Abstract: A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer. A layer of GaAlAs is then provided such that the Ai content and no doping followed by an intrinsic GaAs layer. The intrinsic GaAs layer is the active layer which serves as a channel.
    Type: Grant
    Filed: August 10, 1988
    Date of Patent: April 17, 1990
    Assignee: ITT Corporation
    Inventors: Arthur E. Geissberger, Robert A. Sadler, Gregory E. Menk, Matthew L. Balzan
  • Patent number: 4918510
    Abstract: A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above the surface of the substrate. A polycrystalline silicon sidewall frame is formed at the sidewall of the field oxide and a gate insulator is formed over both the polycrystalline silicon frame and the silicon surface region. A common gate electrode is formed which traverses the frame and the surface region. P-type source and drain regions are formed in the polycrystalline silicon frame on opposite sides of the gate electrode and N-type source and drain regions are formed in the surface region on opposite sides of the gate electrode.
    Type: Grant
    Filed: October 31, 1988
    Date of Patent: April 17, 1990
    Assignee: Motorola, Inc.
    Inventor: James R. Pfiester
  • Patent number: 4918497
    Abstract: The present invention comprises a light emitting diode formed in silicon carbide and that emits visible light having a wavelength of between about 475-480 nanometers, or between about 455-460 nanometers, or between about 424-428 nanometers. The diode comprises a substrate of alpha silicon carbide having a first conductivity type and a first epitaxial layer of alpha silicon carbide upon the substrate having the same conductivity type as the substrate. A second epitaxial layer of alpha silicon carbide is upon the first epitaxial layer, has the opposite conductivity type from the first layer, and forms a p-n junction with the first epitaxial layer. In preferred embodiments, the first and second epitaxial layers have carrier concentrations sufficiently different from one another so that the amount of hole current and electron current that flow across the junction under biased conditions are different from one another and so that the majority of recombination events take place in the desired epitaxial layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: April 17, 1990
    Assignee: Cree Research, Inc.
    Inventor: John A. Edmond
  • Patent number: 4916503
    Abstract: A photo-electric converting device has a plurality of emitters with a non-circular or non-dot shape in order to improve the photo-electric converting efficiency. The distance between the adjacent emitters has a predetermined relation to the average diffusion length of the minority carriers in a base layer in order to further improve the photo-electric conversion efficiency. The device is formed to have groove structures to restrain the photo-electric conversion loss due to reflected light.
    Type: Grant
    Filed: July 8, 1988
    Date of Patent: April 10, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Uematsu, Tadashi Saitoh, Yasuhiro Kida
  • Patent number: 4914488
    Abstract: A compound semiconductor structure in the form of a superlattice film with effectively graded average composition, comprising an alternating lamination of two kinds of layers of different composition to form pairs of layers, the ratio of the thickness of one layer to the thickness of the other in said pairs of layers being gradually varied in the direction of thickness throughout successive pairs, thereby the average composition being effectively graded throughout the pairs. In a hetero-junction field effect transistor, the layer of effectively graded composition is used between a semiconductor layer making low resistance contact with a current-supplying electrode and a semiconductor layer where a two dimensional channel is to be formed. In case of AlGaAs/GaAs system, the Al composition is varied. When the superlattice film is heat-treated, Al in the AlGaAs layer diffuses into the GaAs layer, yielding a film with actually smoothly graded Al mole fraction.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: April 3, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masao Yamane, Tomoyoshi Mishima, Shigeo Goto, Susumu Takahashi, Makoto Morioka
  • Patent number: 4912532
    Abstract: An electro-optical device with a transparent substrate is produced by epitaxially first growing the device layers, followed by that of the transparent substrate layer on an opaque wafer. The opaque wafer is subsequently removed. The device layers have dopants with sufficient low diffusivities that their electronic characteristics are not adversely affected by long exposure to elevated temperature during the growth of the transparent substrate layer. In a liquid phase epitaxy (LPE) method, a repeated temperature cycle technique is used where the temperature is repeatedly raised up each time after cooling to provide a large cooling range for growing a sufficiently thick substrate layer or a series of device layers. In between growths and during the temperature heat-up periods, the device is stored within the LPE reactor. In other embodimens, the device is either temporarily removed from the LPE reactor or is transferred to another reactor.
    Type: Grant
    Filed: August 26, 1988
    Date of Patent: March 27, 1990
    Assignee: Hewlett-Packard Company
    Inventors: Louis W. Cook, Michael D. Camras
  • Patent number: 4910570
    Abstract: A semiconductor photo-detector is disclosed. The inventive photo-detector is especially sensitive to light in the ultraviolet and/or blue portions of the spectrum. The semiconductor body comprising the detector is arranged with a band structure which, through use of a potential threshold, delimits a particular region of the semiconductor body. Illustratively, the particular delimited region is coincident with the region where ultraviolet and/or blue light is absorbed. Charge carriers generated in the delimited region through the absorption of ultraviolet and/or blue light contribute to the output signal. Other wavelengths of light are absorbed in the semiconductor body outside the delimited region. The charged particles generated by the absorption of light outside the delimited region do not contribute to the output signal.
    Type: Grant
    Filed: June 16, 1988
    Date of Patent: March 20, 1990
    Assignee: Landis & Gyr Betriebs AG
    Inventor: Radivoje Popovic
  • Patent number: 4908678
    Abstract: An improved FET is disclosed. The transistor is characterized in that its channel is constituted in the form of a super lattice. The super lattice structure provides a number of square well potential areas through which carriers can pass with little interaction with the gate insulating film.
    Type: Grant
    Filed: September 30, 1987
    Date of Patent: March 13, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4907051
    Abstract: A photocathode with high photoelectric conversion ratio over an extended wavelength range of incident light has a hetero junction formed between thin films of a p-type amorphous silicon alloy having energy gap matching the energy of the incident light and an n-type semiconductor with small work function or large coefficient of secondary electron emission.
    Type: Grant
    Filed: May 12, 1988
    Date of Patent: March 6, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shaw Ehara
  • Patent number: 4907041
    Abstract: A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes is the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantially alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic region thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower dopant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.
    Type: Grant
    Filed: September 16, 1988
    Date of Patent: March 6, 1990
    Assignee: Xerox Corporation
    Inventor: Tiao-Yuan Huang
  • Patent number: 4907060
    Abstract: An encapsulated thermoelectric heat pump, apparatus and method for manufacturing the encapsulated thermoelectric heat pump is disclosed. The encapsulated thermoelectric heat pump includes a plurality of spaced n-type and p-type thermoelectric elements arranged alternatively in rows and columns. The thermoelectric elements having opposing ends operatively connected to first and second metalized ceramic substrates. The first and second metalizations patterned to connect serially the thermoelectric elements. The space between the spaced thermoelectric elements is filled with a microballoon filled epoxy for substantially increasing the strength of the thermoelectric heat pump to withstand a stress of more than 2000 g's.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: March 6, 1990
    Inventors: John L. Nelson, Michael D. Gilley, Dwight A. Johnson
  • Patent number: 4907055
    Abstract: An optical semiconductor device of broad area structure comprising an active region positioned between a p-type semiconductor region having a stripe-like anode electrode and an n-type semiconductor region having a cathode electrode, the anode electrode having a broad stripe width in which the photon density is increased to amplify the light with the aid of injected into the active region dependent on the current density flowing between the anode and cathode electrodes, wherein the density distribution of the injected carriers exhibits Gauss distribution in the widthwise direction of the stripe width. Therefore, it is possible to supply such a current as to produce the density distribution of the injected carriers with no excess or shortage.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: March 6, 1990
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Hidetoshi Shinada
  • Patent number: 4905056
    Abstract: A precision voltage reference incorporating at least one superlattice resonant tunneling diode and support electronics. The precision voltage reference is stable as to temperature and radiation.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: February 27, 1990
    Inventors: Dale F. Berndt, Andrzej Peczalski
  • Patent number: 4905063
    Abstract: A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
    Type: Grant
    Filed: June 21, 1988
    Date of Patent: February 27, 1990
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Fabio Beltram, Federico Capasso, Roger J. Malik, Nitin J. Shah
  • Patent number: 4901124
    Abstract: A conductivity modulated MOSFET is composed of a MOSFET formed according to SOI technique utilizing two polycrystalline silicon layers deposited on a semiconductor substrate through an oxide film, and a vertical bipolar transistor formed within the semiconductor substrate. Therefore, electrons and positive holes pass through different passages respectively, and any parasitic thyristor is not formed as in the conventional conductivity modulated MOSFET with a MOSFET built in the semiconductor substrate, and thus there is no possibility of causing the latch up phenomenon.
    Type: Grant
    Filed: April 18, 1989
    Date of Patent: February 13, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasukazu Seki
  • Patent number: 4899200
    Abstract: A high-speed heterostructure planar integrated circuit includes a planar photodetector together with a transistor (either a Modulation-Doped Field Effect Transistor or a lateral p-n-p bipolar transistor). The planar photodetector includes a bottom confinement layer of a wide bandgap material, a heavily doped first conductivity-type buried layer over the bottom confinement layer, a relatively undoped higher index of refraction layer overlying the buried layer, a top confinement layer of wider bandgap material which has a lower index of refraction, a first vertical contact region of first conductivity type which extends downward to make electrical contact with the buried layer, and a second contact region of second conductivity type spaced laterally from the first contact region and extending through the top confinement layer and a portion of the undoped layer.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: February 6, 1990
    Assignee: Regents of the University of Minnesota
    Inventors: Michael Shur, John G. Simmons
  • Patent number: 4897699
    Abstract: Disclosed is an optoelectronic device implanted on a silicon substrate and comprising, in particular, on this substrate, a set of matching layers on which there is made a first confinement layer based on indium phosphide, an active layer based on Ga.sub.x In.sub.1-x As.sub.1-y and a second active layer of indium phosphide.
    Type: Grant
    Filed: September 21, 1988
    Date of Patent: January 30, 1990
    Assignee: Thomson-CSF
    Inventors: Manijeh Razeghi, Robert Blondeau, Franck Omnes, Martin Defour, Gerard Doriath
  • Patent number: 4896200
    Abstract: A semiconductor-based radiation detector comprising a semiconductor substrate and an amorphous semiconductor layer formed on one surface of the substrate, one electrode being applied to the substrate and one to the amorphous layer, the electrodes formed on the amorphous semiconductor layer consisting of closely spaced, interconnected conductive strips which are substantially uniformly arranged over the entire radiation-incident surface of the amorphous semiconductor layer whereby the electrostatic capacitance appearing between the electrodes of the detector is significantly reduced without significantly changing the area of the detector that responds to radiation.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: January 23, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasukazu Seki, Noritada Sato, Masaya Yabe
  • Patent number: 4896202
    Abstract: An edge illuminated impurity band conduction detector includes an extrinsic semiconducting IR-active layer with a first conductivity type impurity concentration high enough to create an impurity energy band. An intrinsic semiconducting blocking layer includes first and second conductivity type impurity concentration low enough that substantially no charge transport occurs by an impurity conduction mechanism. The IR-active and blocking layers are positioned between first and second contacts such that an electrical potential applied to the contacts creates an electric field across the layers. The detector is oriented such that the electromagnetic energy impinges on an edge of the IR-active layer and propagates in the IR-active layer in a direction substantially orthogonal to the applied electric field, the IR-active layer extending in the orthogonal direction for at least the absorption length of the electromagnetic energy.
    Type: Grant
    Filed: June 20, 1988
    Date of Patent: January 23, 1990
    Assignee: Rockwell International Corporation
    Inventors: Ramasesha Bharat, Michael D. Petroff
  • Patent number: 4894703
    Abstract: A back-illuminated InGaAs photodiode is described in which a double layer of silicon nitride on the front surface serves several functions; both layers passivate the surface; an opening in the lower layer provides a diffusion mask for forming the p-n junction; and a narrower opening in the upper silicon nitride layer provides a deposition mask for forming a restricted area contact. In order to reduce strain near the junction, and hence reduce leakage currents and enhance reliability, the contact geometry has a narrow pedestal portion which contacts the surface in a zone remote from the junction edges and has a wider cap portion which is formed on the pedestal portion to seal the surface from the introduction of contaminants.
    Type: Grant
    Filed: August 20, 1985
    Date of Patent: January 16, 1990
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Mahmoud A. E. Hamamsy, Stephen R. Forrest, John R. Zuber