Abstract: A solid state image sensor including a plurality of sensing cells, each formed of a switching transistor and a thin film sensing device, arranged in a line or a matrix. The switching transistor is a thin film transistor (TFT) of polycrystalline silicon and the thin film sensing device utilizes a layer of amorphous silicon formed on a lower electrode which is electrically connected to the drain of the switching.

Abstract: The I/O ports of a packaged IC includes a plurality of optical conduits in the package adjacent electro-optical transmitters and receivers throughout the die spaced from the periphery of the die. The method of assembling the die in the package includes using optical transmitters on the die to align the top of the package and the optical conduits to the die which was previously mounted in the base of the package.

Abstract: A thin-film transistor comprising an insulating substrate; an opaque metal gate electrode disposed on a portion of said insulating substrate; a gate insulating layer disposed on said insulating substrate including said gate electrode; an a-Si semiconductor film disposed on the portion of said gate insulating layer, said a-Si semiconductor film having been formed to attain self-alignment with respect to said gate electrode; a-Si contact films constituting source and drain regions, respectively, with a gap therebetween disposed on said a-Si semiconductor film, the outer end of each of said contact films being formed to attain self-alignment with respect to said gate electrode; source and drain electrodes, respectively, disposed on said source and drain regions, the thickness of each of said a-Si semiconductor film and said a-Si contact film being 100 .ANG. or more and the total amount of thicknesses thereof being 1,000 .ANG. or less.

Abstract: A low capacitance, high performance semiconductor device is described having a sidewall emitter wherein the emitter width is relatively small (approximately 0.5 micrometers). This enables a small emitter-base interface which reduces capacitance. Additionally, the regions of the base and collector near their interface are lightly doped so that collector-base capacitance is greatly reduced.

Abstract: The MOS switch described herein includes first and second MOS devices serially connected in a common substrate. Each device includes source, drain and channel regions which are biased to conduction in series between input and output terminals of the switch in its "on" or conductive state. The novel device connection prevents any pn junction in either MOS device from becoming forward biased. This action, in turn, prevents any parasitic bipolar transistor action in either device after the MOS switch turns off. This latter operational feature eliminates the need for a fourth terminal through which a DC bias potential is applied to either MOS device, and thus undesirable shifts in threshold voltage produced by such DC bias are eliminated.

Abstract: This circuit comprising conductive lines for the transfer of high-speed signals is formed from a semiconductor material in the presence of a two-dimensional gas 2DG between two of its layers (3 and 4). By a suitable choice of the conditions of the temperature and of the magnetic field B, it is then made superconducting, thus permitting the transport of high-speed signals without delay and without distortion of the signals.

Abstract: A high performance III-V heterostructures exhibiting quantum size effects has been achieved in MODCVD utilizing in situ grown (IV).sub.x (III-V).sub.1-x alloys, where (IV) is a group IV element comprising Si, Ge, C or Sn or admixtures thereof and (III-V) is a group III-V binary, trinary, quaternary or pentad compound or alloy such as, for example, GaAs, AlAs, GaAlAs, GaAlAsP, InGaAlP, InAlAsP or InGaAlAsP. Specific examples are (Si.sub.2).sub.x (GaAs).sub.1-x, which is an alloy that functions as a barrier when grown in situ in a GaAs active region of a heterostructure and (Ge.sub.2).sub.x (GaAs).sub.1-x, which is an alloy that functions as a quantum well when grown in situ in GaAs or GaAlAs active region (e.g. highest refractive index and narrowest bandgap) of a heterostructure. The disclosure further relates to the utilization of a nucleating or catalytic process wherein a small amount of a cluster collector or anchorage component, e.g.

Abstract: A field effect transistor has its drain and source regions connected between one of the two supply pads of an operative integrated circuit, the gate of the field effect transistor being connected to the other pad such that the gate is negatively biased during reverse battery to prevent current flow through the circuit in this condition and, hence, to prevent destruction of the circuit. The FET is sized to have minimal voltage drop during normal, forward battery operation of the circuit. The FET can be implemented as either an N-channel or a P-channel device.

Abstract: A photosensor comprises an insulating substrate, an electrode, a photoconductor layer composed of a hydrogenated amorphous silicon semiconductor layer obtained by the glow discharge decomposition of monosilane gas, a junction stabilizing layer composed of a boron-containing hydrogenated amorphous silicon semiconductor which is obtained by the glow discharge decomposition of a mixed gas of monosilane and diborane, a transparent electrode and a transparent protective layer, these elements being laminated in that order. The insertion of the junction stabilizing layer between the photoconductor layer and the transparent electrode greatly improves the dark current characteristic. The electrode, the photoconductor layer and the junction stabilizing layer can be divided in correspondence with each picture element, thereby improving the resolution of the photosensor.

Abstract: In a thin-film transistor array, a plurality of gate buses and a plurality of source buses are formed on a substrate in such a manner that said gate buses are intersected with said source buses at crossover portions, and a plurality of thin-film transistors are formed on the substrate adjacent to the crossover portion, which are connected to the gate buses and source buses for a driving purpose.Furthermore, an auxiliary bus is formed on either the gate buses, or source buses, shortcircuited portions of which are cut out by means of laser trimming so as to conduct the gate buses or source buses.

Abstract: A semiconductor cathode is realized with the aid of a pin structure in which the intrinsic semiconductor region includes a first region with a small band distance and a second region with a large band distance. Consequently, at a sufficient reverse voltage, electrons (6) are generated in the first region (6) which electrons tunnel from the valence band to the conduction band and have a sufficient potential energy to be emitted from the semiconductor body.

Abstract: A semiconductor integrated circuit such as a master slice LSI, wherein a gate region and input/output cell regions in the periphery thereof are composed entirely of logic-constituting elements servable as input/output cells. The logic-constituting cells in the whole of the input/output cell regions and any desired portion of the gate region are formed as input/output cells in the slice process of production.

Abstract: In a thin film transistor which has an active layer formed between source and drain electrodes, a gate insulating film formed in contact with the active layer, and a gate electrode formed in contact with the gate insulating film, the photoconductivity of the active layer is reduced by forming the active layer of amorphous silicon carbide (a-Si.sub.1-x C.sub.x) whose carbon content x is greater than 0.1.

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: Enhanced density of electrical and/or mechanical interconnections between adjacent wafers within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions, is attained by utilizing laser assisted chemical vapor deposition to fabricate precisely configured metal posts which serve as such interconnections.

Abstract: A photodetector which operates at a cryogenic temperature by utilizing superconductivity is disclosed. A plurality of mutually spaced-apart superconducting layers are formed in such a manner as to be in contact with a semiconductor layer at least one of the surfaces of which is an incidence surface of light, and means capable of accumulating carriers in the semiconductor layer is disposed.A photodetector having high performance can thus be obtained and can be used as an interface of a system at a cryogenic temperature.

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprises rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Abstract: A MOSFET utilizes a buried channel structure comprising a buried channel between a source electrode and a drain electrode. The device also comprises a gate electrode made of material whose Fermi level is located between a conduction band and a valency band of a semiconductor. An impurity concentration in the substrate is relatively high because of buried channel structure.

Abstract: A process for production of a hydrogenated amorphous silicon film of a silicon compound containing at least one element selected from the group consisting of hydrogen and halogens and having a photosensitivity of not less than 0.1 erg/cm.sup.2 at 780 nm, which comprisessupplying a gas selected from the group consisting of SiH.sub.4, SiF.sub.4 and Si.sub.2 H.sub.6 into a discharge space, andsubjecting the gas to glow discharge within the discharge space having a gradient discharge intensity.The present invention provides an a-SiH film which has a remarkable high sensitivity in a long wavelength region with maintaining a high photosensitivity in a visible light region, and has a remarkable less defect density, and the process for production of such film in a high deposition rate.

Abstract: A selective contact to a NIPI doping superlattice having a trap free (or low trap density) contact in contact with the layers of the superlattice. In a NIPI superlattice, the trap free region is a doped region that can be produced: by diffusion of dopant ions from a doped metal contact; by overdoping of the edges of the superlattice; or by overgrowth of the edges of the superlattice with a doped material that is trap free.